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US 2002/0163000 A1Published application
Semiconductor device and method of fabricating the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorSHUNPEI YAMAZAKI
Life of this patent
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Abstract
Reliability of crystalline TFTs is improved in a large area integrated circuit typified by an active matrix type liquid crystal display device. In TFTs having an LDD structure, a region whose LDD region overlaps with a gate electrode and a region not overlapping with the gate electrode are fabricated inside one TFT. To accomplish this structure, n-channel TFTs are fabricated in non-self-alignment whereas p-channel TFTs are fabricated in self-alignment.
Claims57
A semiconductor device comprising:
- a substrate having an insulating surface;
- a semiconductor layer formed over said substrate;
- a gate insulating film formed in contact with said semiconductor layer;
- a gate electrode formed in contact with said gate insulating film;
- and
- a gate wiring connected to said gate electrode,
- wherein said gate electrode and said gate wiring comprise a first conductor layer formed in contact with said gate insulation film,
- wherein said semiconductor layer comprises
- a channel formation region,
- a first impurity region of one conductivity type and
- a second impurity region of one conductivity type that is sandwiched between said channel formation region and said first impurity region, and is in contact with said channel formation region, and
- wherein at least a part of said second impurity region overlaps with said gate electrode.
9 more elements
A semiconductor device having a matrix circuit comprising n-channel thin film transistors,
- wherein a gate electrode of said n-channel thin film transistors and a gate wiring connected to said gate electrode comprise a first conductor formed in contact with a gate insulating film,
- wherein a semiconductor layer of said n-channel thin film transistors comprises
- a channel formation region,
- a first impurity region of one conductivity type and
- a second impurity region of said one conductive type that is sandwiched between said channel formation region and said first impurity region and is in contact with said channel formation region, and
- wherein a part of said second impurity region of said one conductivity type overlaps with said gate electrode.
3 more elements
A semiconductor device having at least a CMOS circuit comprising n-channel thin film transistors and p-channel thin film transistors,
- wherein a gate electrode of said n-channel thin film transistors and a gate wiring connected to said gate electrode comprise a first conductor layer formed in contact with a gate insulating film;
- wherein a semiconductor layer of said n-channel thin film transistors comprises
- a channel formation region,
- a first impurity region of one conductivity type and
- a second impurity region of one conductivity type that is sandwiched between said channel formation region and said first impurity region and is contact with said channel formation region, and
- wherein a part of said second impurity region of said one conductivity type overlaps with said gate electrode.
3 more elements
A semiconductor device comprising
- a matrix circuit comprising n-channel thin film transistors and
- a CMOS circuit comprising n-channel thin film transistors and p-channel thin film transistors:
- wherein a gate electrode of said n-channel thin film transistors and a gate wiring connected to said gate electrode comprise a first conductor layer formed in contact with a gate insulation film,
- wherein a semiconductor layer of said n-channel thin film transistors comprises
- a channel formation region,
- a first impurity region of one conductivity type and
- a second impurity region of said one conductivity type that is sandwiched between said channel formation region and said first impurity region and is in contact with said channel formation region, and
- wherein a part of said second impurity region of said one conductivity type overlaps with said gate electrode.
5 more elements
A semiconductor device having a first n-channel thin film transistor and a second n-channel thin film transistor in one pixel,
- wherein a gate electrode of said first and second nchannel thin film transistors and a gate wiring connected to said gate electrode comprise a first conductor layer formed in contact with a gate insulating film;
- wherein a semiconductor layer of said first n-channel thin film transistor comprises
- a channel formation region,
- a first impurity region of one conductivity type and
- a second impurity region of said one conductivity type, that is sandwiched between said channel formation region and said first impurity region, and is in contact with said channel formation region,
- wherein a part of said second impurity region of said one conductivity type overlaps with said gate electrode;
- and
- wherein a semiconductor layer of said second n-channel thin film transistor comprises
- a channel formation region,
- a first impurity region of one conductivity type and
- a second impurity region of said one conductivity type that is sandwiched between said channel formation region and said first impurity region and is in contact with said channel formation region,
- wherein said second impurity region of said one conductivity type overlaps with said gate electrode.
9 more elements
A semiconductor device including an n-channel thin film transistor and a p-channel thin film transistor in one pixel:
- wherein a gate electrode of said n- and p-channel thin film transistors and a gate wiring connected to said gate electrode comprise a first conductor layer formed in contact with a gate insulating film;
- wherein a semiconductor layer of said n-channel thin film transistor comprises
- a channel formation region,
- a first impurity region of one conductivity type and
- a second impurity region of said one conductivity type that is sandwiched between said channel formation region and said first impurity region of said one conductivity type, and is in contact with said channel formation region;
- wherein a part of said second impurity region of said one conductivity type overlaps with said gate electrode;
- wherein a semiconductor layer of said p-channel thin film transistor comprises
- a channel formation region,
- a third impurity region of a conductivity type opposite to said one conductivity type,
- wherein said third impurity region is disposed outside said gate electrode.
7 more elements
A semiconductor device including an n-channel thin film transistor and a p-channel thin film transistor in one pixel:
- wherein a gate electrode of said n- and p-channel thin film transistors and a gate wiring connected to said gate electrode comprise a first conductor layer formed in contact with a gate insulating film;
- wherein a semiconductor layer of said n-channel thin film transistor comprises
- a channel formation region,
- a first impurity region of one conductivity type and
- a second impurity region of said one conductivity that is sandwiched between said channel formation region and said first impurity region of said one conductivity type, and is in contact with said channel formation region,
- wherein a part of said second impurity region of said one conductivity type overlaps with said gate electrode;
- wherein a semiconductor layer of said p-channel thin film transistor comprises
- a channel formation region and
- a third impurity region of a conductivity type opposite to said one conductivity type,
- wherein a part of said third impurity region overlaps with said gate electrode.
7 more elements
A method of fabricating a semiconductor device comprising the steps of:
- forming a semiconductor layer over a substrate having an insulation surface;
- patterning said semiconductor layer to form at least a first and a second island semiconductor layers;
- forming a gate insulation film in contact with said first and second island semiconductor layers;
- adding an impurity element of one conductivity type into a selected region of said first island semiconductor layer, and forming a second impurity region;
- forming a first conductor layer in contact with said gate insulation film;
- forming a second gate electrode overlapping with said second island semiconductor layer by patterning said first conductor layer;
- adding an impurity element of a conductivity type opposite to said one conductivity type into a selected region of said second island semiconductor layer, and forming a third impurity region;
- forming a first gate electrode overlapping with said first island semiconductor layer by patterning said first conductor layer;
- and
- adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a first impurity region.
7 more elements
A method of fabricating a semiconductor device comprising the steps of:
- forming a semiconductor layer over a substrate having an insulation surface;
- patterning said semiconductor layer to form at least a first and a second island semiconductor layers;
- forming a gate insulation film in contact with said first and second island semiconductor layers;
- adding an impurity element of one conductivity type into a selected region of said first island semiconductor layer and forming a second impurity region;
- forming a first conductor layer in contact with said gate insulation film;
- forming a first gate electrode overlapping with said first island semiconductor layer and a second gate electrode overlapping with said second island semiconductor layer by patterning said first conductor layer;
- adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a first impurity region;
- and
- adding an impurity element of a conductivity type opposite to said one conductivity type into a selected region of said second island semiconductor layer, and forming a third impurity region.
6 more elements
A method of fabricating a semiconductor device comprising the steps of:
- forming a semiconductor layer over a substrate having an insulation surface;
- patterning said semiconductor layer to form at least a first and a second island semiconductor layers;
- forming a gate insulation film in contact with said first and second island semiconductor layers;
- adding an impurity element of a conductivity type opposite to said one conductivity type into a selected region of said second island semiconductor layer, and forming a third impurity region;
- adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a second impurity region;
- forming a first conductor layer in contact with said gate insulation film;
- forming a first gate electrode overlapping with said first island semiconductor layer and a second gate electrode overlapping with said second island semiconductor layer from said first conductor layer;
- and
- adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a first impurity region.
6 more elements
A method of fabricating a semiconductor device comprising the steps of:
- forming a semiconductor layer over a substrate having an insulation surface;
- patterning said semiconductor layer to form at least a first and a second island semiconductor layers;
- forming a gate insulation film in contact with said first and second island semiconductor layers;
- adding an impurity element of a conductivity type opposite to said one conductivity type into a selected region of said second island semiconductor layer, and forming a third impurity region;
- adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a first impurity region;
- adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a second impurity region;
- forming a first conductor layer in contact with said gate insulation film;
- and
- forming a first gate electrode overlapping with said first island semiconductor layer and a second gate electrode overlapping with said second island semiconductor layer from said first conductor layer.
6 more elements
A method of fabricating a semiconductor device comprising the steps of:
- forming a semiconductor layer over a substrate having an insulation surface;
- patterning said semiconductor layer to form at least first and second island semiconductor layers;
- forming a gate insulation film in contact with said first and second island semiconductor layers;
- adding an impurity element of one conductivity type into a selected region of said first island semiconductor layer, and forming a first impurity region;
- adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a second impurity region;
- forming a first conductor layer in contact with said gate insulation film;
- forming a second gate electrode overlapping with said second island semiconductor layer from said first conductor layer;
- adding an impurity element of a conductivity type opposite to said one conductivity type into a selected region of said second island semiconductor layer, and forming a third impurity region;
- and
- forming a first gate electrode overlapping with said first island semiconductor layer from said first conductivity type.
7 more elements
A method of fabricating a semiconductor device comprising the steps of:
- forming a semiconductor layer over a substrate having an insulation surface;
- patterning said semiconductor layer to form at least first and second island semiconductor layers;
- forming a gate insulation film in contact with said first and second island semiconductor layers;
- adding an impurity element of one conductivity type into a selected region of said first island semiconductor layer, and forming a first impurity region;
- adding an impurity element of a conductivity type opposite to said one conductivity type into a selected region of said second island semiconductor layer, and forming a third impurity region;
- adding an impurity element of said one conductivity type into a selected region of said first island semiconductor layer, and forming a second impurity region;
- forming a first conductor layer in contact with said gate insulation film;
- and
- forming a first gate electrode overlapping with said first island semiconductor layer and a second gate electrode overlapping with said second island semiconductor layer from said first conductor layer.
6 more elements
Dependencies are inferred from the claim text.