CMOS photodiode having reduced dark current and improved light sensitivity and responsivity

A light-sensing diode fabricated in a high resistivity semiconductor substrate of a first conductivity type, said substrate having a surface protected by an insulator, comprising:

• a first well of the opposite conductivity type in said substrate having a geometry such that portions of its junctions extend in two different planes under said surface, oriented approximately parallel to said surface;
• and other portions of its junctions having sidewall portions, said junctions terminating at said surface under said insulator;
• at least one contact to said first well, formed at said surface through said insulator, for applying bias across said first well junctions;
• a second well of said first conductivity type fabricated in said substrate, at least partially surrounding said sidewalls of said first well, forming a junction with said first well;
• and
• contacts for applying electrical bias across said second well and substrate junctions.

A semiconductor diode having minimal surface-generated junction leakage current, comprising:

• a semiconductor substrate of a first conductivity type, said substrate having a surface protected by an insulator;
• a region of the opposite conductivity type in said substrate located so that the junctions reach said surface under said protective insulator, thereby defining the surface area portion of said region;
• at least one extension of said region positioned along said surface under said insulator into said substrate such that portions of said junctions are buried and said surface area portion is minimized;
• and
• contacts for applying electrical bias across said junctions.

A method of fabricating a light-sensing diode, having minimal surface-generated junction leakage current, in a high resistivity semiconductor substrate of a first conductivity type, comprising the steps of:

• forming protective isolation regions into the surface of selected portions of said semiconductor;
• implanting, at high energy, ions of said first conductivity type into said semiconductor to form a well of said first conductivity type shaped as an annulus such that a selected central portion of said semiconductor remains unimplanted;
• implanting, at high energy, ions of the opposite conductivity type into said central portion to form a well having side walls surrounded by said well of said first conductivity type;
• implanting, at low energy and high dose, ions of said first conductivity type into at least one selected portion of said well of said opposite conductivity type to form, under and near said surface, a region of compensated conductivity, thereby extending along said surface under said insulator said well of said first conductivity;
• rapidly annealing said ion implants;
• depositing over portions of said surface a layer of insulating material suitable as gate dielectric;
• forming gates of poly-silicon or other conductive material deposited onto said insulating layer;
• forming source and drain regions to complete said diode;
• and
• forming contact metallizations at said source and drain regions.

A method of fabricating a semiconductor diode having minimal surface-generated junction leakage current, comprising the steps of:

• providing a high resistivity semiconductor substrate of a first conductivity type, said substrate having an insulated surface;
• forming a first well of the opposite conductivity type in said substrate to form a junction within said substrate remote from said surface, and further creating well sidewall portions having junctions which reach said surface under said insulator, thereby defining the surface area portion of said first well;
• forming a second well of said first conductivity type in said substrate, said second well having at least one extension into said first well along said surface under said insulator well, creating buried near-the-surface junctions, as well as sidewall junctions, with said first well, thereby constricting said first well surface area;
• and
• forming contacts for applying electrical bias across said junctions.