Process for fabricating a component, such as a capacitor in an integrated circuit, and integrated-circuit component

A method for fabricating a component in an integrated circuit, above a surface onto which first and second primary electrical connection vias open out, the vias being spaced apart and connected to each other below the surface and at a predetermined distance from the surface, the method comprising:

• depositing a first layer made of an electrically non-conducting material on a surface;
• forming a main hole in this first layer above a first connection via;
• depositing a second layer made of an electrically conducting material, covering one or more walls of the main hole;
• removing the second layer, leaving the electrically conducting material only in the main hole so as to constitute a first electrode in a form of a cup in this main hole;
• forming a dielectric at least on an inner surface of the cup;
• depositing a third layer of a electrically conducting material, filling the cup;
• removing the third layer, leaving the electrically conducting material in the cup so as to constitute a second electrode separated from the first electrode by the dielectric;
• depositing a fourth layer made of an electrically non-conducting material;
• forming a first secondary hole passing through the fourth layer and reaching a top surface of the second electrode and a second secondary hole passing through the fourth layer and the first layer, at a predetermined distance from the main hole, and reaching a top surface of the second via;
• and
• filling the first secondary hole and the second secondary hole with an electrically conducting material so as to form connection vias for the first electrode and second electrode.