Embedded microprocessor emulation method
AssigneesDolphin Integration, Raisonance
InventorsGauthier Barret, Jean-Francois Pollet, Francis Lamotte
Life of this patent
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Abstract
A method of emulation or functional testing of a first microprocessor in its functional environment including one or several peripherals and at least one internal bus of communication between this first microprocessor and its peripherals, from a second microprocessor, consisting of deactivating the first microprocessor, using the communication bus(es) to communicate between the two microprocessors and the peripheral(s), and activating the second microprocessor, wherein the first microprocessor communicates with the second microprocessor over a series link and wherein the second microprocessor is realized by a simulation model.
Claims9
A method of emulation or functional testing of a first microprocessor (34) in its functional environment including one or several peripherals (32, 342) and at least one internal bus (36) of communication between this first microprocessor and its peripherals, from a second microprocessor (10), consisting of:
- deactivating the first microprocessor;
- using the communication bus(es) (36) to communicate between the two microprocessors and the peripheral(s);
- and
- activating the second microprocessor;
- wherein the first microprocessor (34) communicates with the second microprocessor (10) over a series link (2), and wherein the second microprocessor (10) is realized by a simulation model.
A circuit (3) integrating a first microprocessor (34), peripherals (32, 342), and at least one first bus (36) of communication between this first microprocessor and its peripherals, including means for deactivating a bare core (31) of the first microprocessor and for making accessible the first bus from outside of the circuit, wherein the bare core (31) of the first microprocessor (34) integrates at least one first multiplexer (70) to control the first bus(es) (36), selecting either a second bus coming from within the bare core, or a third bus coming from a circuit of series interface (74) with the outside of the circuit.
An emulator of a first microprocessor (34), including a microprocessor core (101) functionally equivalent to that of the first microprocessor and means for using the peripherals and buses of the first microprocessor in an emulation phase.
Dependencies are inferred from the claim text.