Apparatus and method for processor performance monitoring
AssigneeSun Microsystems, Inc.
InventorHari K. Ravichandran
Life of this patent
Estimating the term…
Abstract
The technology of the present invention pertains to an apparatus and method for implementing a hardware-based performance monitoring mechanism for use in analyzing the behavior of a program module. The apparatus includes probe logic hardware that monitors the program's behavior in executing memory reference instructions. The probe logic hardware generates several probe signals which are transmitted to a performance monitor circuit when certain events occur. In an embodiment of the present invention, these events can be TLB or cache misses. The performance monitor circuit affixes a time stamp to the probe data and stores the time-stamped probe data in a temporary memory device until the data is stored in a magnetic storage device.
Claims12
An apparatus for monitoring an execution behavior of a program, comprising:
- a processor for executing a plurality of instructions;
- a probe logic unit in communication with the processor that generates probe signals representative of memory access misses occurring in the processor;
- a performance monitor circuit element that receives the probe signals and associates a temporal identifier signal with the probe signals;
- and
- a memory for storing the temporal identifier signal and the probe signals.
A method for monitoring an execution of a program, the method comprising the steps of:
- (1) obtaining a first instruction including a first address;
- (2) searching a first memory device for an entry associated with the first address;
- (3) when the entry in the first memory device does not exist, generating at least one probe signal indicating a miss entry in the first memory device;
- (4) generating a temporal identifier signal that is associated with the probe signals;
- and
- (5) storing the temporal identifier signal and the probe signals in memory.
Dependencies are inferred from the claim text.