US 2002/0162086 A1 · RTL annotation tool for layout induced netlist changes

Abstract

A Register Transfer Language (RTL) annotation software tool that: (1) automatically calculates new RTL of a circuit to facilitate subsequent RTL level Engineering Change Orders (ECOs) on a circuit where gate level changes have occurred during layout; and (2) automatically calculates a gate level netlist that corresponds to the RTL ECO which can be fed to modern layout tools with minimal disruption to the existing layout. In a preferred embodiment, the tool is software driven, iterative, and tracks any changes that need to be made for any given circuit described by a hardware description language (HDL) though a series of intermediate and preliminary data files. The software receives input in the way of user input, constraints, and an RTL description for a pre-ECO circuit, and outputs the post-layout annotated RTL description. Subsequent ECOs are taken as input from the user in the form of a modified annotated RTL description and the software produces a corresponding gate level netlist for the ECO circuit, all the while preserving as much of the data generated during this process to avoid wasteful duplication of effort.

Claims39

Dependent claims

In a software system, an Electronic Design Automation (EDA) software application program for facilitating an Engineering Change Order (ECO), said software program comprising:

a circuit description described in a hardware description language (HDL) comprising a pre-ECO circuit description comprising a pre-ECO Register Transfer Level (RTL) netlist, and a ECO circuit description comprising an ECO circuit RTL netlist, said ECO circuit RTL netlist representing said pre-ECO RTL netlist modified by an ECO;
an ECO RTL netlist software module for generating said ECO RTL netlist;
a final ECO gate-level netlist synthesis software module for generating and outputting a final ECO gate-level netlist, said ECO gate-level netlist corresponding to said ECO RTL netlist and describing said ECO circuit.

A computer system running a Electronic Design Automation (EDA) software tool application comprising:

a computer having a processor and memory;
a software application, run by said computer processor, and residing in said computer memory;
data comprising a circuit description described in a hardware description language (HDL), said circuit description comprising a pre-ECO circuit description and an ECO circuit description, said ECO circuit description being said pre-ECO circuit description modified by an Engineering Change Order (ECO);
a pre-ECO constraints file that specifies pre-ECO constraints for said pre-ECO circuit description, and a ECO constraints file that specifies ECO constraints for said ECO circuit;
said software application comprising a plurality of software function modules comprising:
a pre-ECO circuit register transfer level (RTL) netlist software module within said application for generating a pre-ECO RTL netlist description of said pre-ECO circuit description, said pre-ECO RTL netlist conforming to said pre-ECO constraints file;
a pre-ECO circuit gate-level netlist software module within said application for generating a gate-level netlist description of said pre-ECO circuit, said pre-ECO circuit gate-level netlist conforming to said pre-ECO constraints file;
an ECO RTL netlist software module for generating an ECO RLT netlist description of said ECO circuit, said ECO RTL netlist conforming to said ECO constraints file;
a final ECO gate-level netlist software module for generating and outputting a final gate level netlist of said ECO circuit that corresponds to said ECO RTL netlist and that satisfies said ECO constraints file.

6 more elements

A software method of generating Register Transfer Level (RTL) and gate-level netlists in response to an ECO to a circuit, comprising the steps of:

generating a hardware description language (HDL) description of a circuit, said HDL circuit description comprising a pre-ECO circuit description and an ECO circuit description, said ECO circuit description being said pre-ECO circuit description modified by an Engineering Change Order (ECO);
generating an ECO circuit RTL netlist description of said ECO circuit;
generating an ECO circuit preliminary gate-level netlist description of said ECO circuit;
comparing said ECO circuit RTL netlist to said ECO circuit preliminary gate-level netlist to extract and generate ECO prelayout correspondence points;
reading data comprising a ECO constraints file representing constraints for said ECO circuit;
comparing said ECO prelayout correspondence points with said ECO constraints to verify said ECO constraints match said ECO prelayout correspondence points;
generating a ECO circuit final gate-level netlist of said ECO circuit, said final gate-level netlist representing said ECO circuit satisfying said ECO constraints file.

4 more elements

Dependencies are inferred from the claim text.

RTL annotation tool for layout induced netlist changes

Life of this patent

RTL annotation tool for layout induced netlist changes

Life of this patent

Abstract

Claims39