Method and system for displaying VLSI layout data

A method of viewing a VLSI layout design, comprising:

• loading a VLSI layout design into a first memory;
• determining a number of LODs from a base representation level to a top level of a chip pyramid according to the first representation;
• determining a first transition threshold and second transition threshold at a higher LOD from the first transition threshold that subdivide the chip pyramid into three sections;
• and
• displaying a representation of the VLSI layout design using a first displaying technique below the first transition threshold, a second displaying technique between the two transition thresholds and a third displaying technique above the second transition.

A method of rendering a viewable representation of an integrated circuit (IC) layout, comprising:

• loading a canonical form of the IC layout into a first memory;
• determining a chip pyramid structure having a plurality of levels of detail (LOD) from a base LOD to a top LOD according to the canonical form of the IC layout;
• determining hierarchy data for selected sub-designs in the canonical form and storing the hierarchy data in a second memory;
• determining a selected LOD in the chip pyramid to display the IC layout according to an input viewpoint;
• displaying the IC layout using stored sub-images of selected portions of the canonical form when the selected LOD is above a first threshold;
• and
• displaying the IC layout by using the canonical form to directly display polygons when the selected LOD is below the first threshold.