Automated wiring pattern layout method

A semiconductor device, comprising:

• a substrate;
• a first interlayer insulating layer on the substrate;
• a first metal wiring on the first interlayer insulating layer, the first metal wiring having a width of W, extending in a first direction and having a first end portion;
• a second interlayer insulating layer covering the first metal layer and the first interlayer insulating layer;
• a second metal wiring on the second interlayer insulating layer, the second metal wiring extending in a direction perpendicular to the first metal wiring, and having an L-shaped bent region with a length of at least 2 W but no greater than 5 W overlapping the first metal wiring end;
• and
• a VIA contact passing through the second interlayer insulating layer, the VIA contact connecting the first metal wiring end and the L-shaped bent region of the second metal wiring.

A computer readable recording medium, which is recorded with a program for causing an automated layout device to operate, the program comprising:

• generating a first wiring pattern with width W extending in a first direction;
• generating a second wiring pattern with width W extending in a direction perpendicular to the first wiring pattern in a manner such that the end portion thereof ends at the end portion of the first wiring pattern;
• generating an overlapping region by bending an end portion of either one of the first or the second wiring pattern at a right angle, extending to a length of at least 2 W but no greater than 5 W, and overlaying the first wiring pattern and the second wiring pattern;
• and
• generating at the overlapping region a rectangular-shaped VIA pattern having an aspect ratio of at least two but no greater than five.

A wiring pattern optical correction method, comprising:

• generating a first wiring pattern extending in a first direction;
• generating a second wiring pattern extending diagonal to the first wiring pattern so that the end portion of the second wiring pattern overlaps the end portion of the first wiring pattern;
• designating a parallelogram-shaped overlapping region, having the intersection of a centerline along the length of the first wiring pattern and a centerline along the length of the second wiring pattern as a center point, at the end section where the first wiring pattern and second wiring pattern overlap;
• generating an expansion region, being obtained by expanding in the same direction the respective outsides of the two edges along the first wiring pattern and also the respective outsides of the two edges along the diagonal second wiring pattern of the parallelogram-shaped overlapping region;
• generating a merge pattern by merging the second wiring pattern and the expansion region;
• and
• dividing the merge pattern into a plurality of regions along the same direction.

A wiring pattern layout method, comprising:

• generating a first wiring pattern with a width W extending in a first direction;
• generating a second wiring pattern with a width wider than width W of the first wiring pattern extending in a direction diagonal to the first wiring pattern so that end portion of the second wiring pattern overlaps the end portion of the first wiring pattern;
• and
• generating along the first wiring pattern, at the intersection of a centerline along the length of the first wiring pattern and a centerline along the length of the second wiring pattern, a rectangular-shaped first VIA pattern having an aspect ratio of at least two so that the center point thereof matches the intersection.

A wiring pattern optical correction method, comprising:

• generating a first wiring pattern extending in a first direction;
• generating a second wiring pattern extending diagonal to the first wiring pattern so the end portion of the second wiring pattern overlaps the end portion of the first wiring pattern;
• designating at the end section where the first wiring pattern and the second wiring pattern overlap a parallelogram-shaped overlapping region, which has the intersection of a centerline along the length of the first wiring pattern and a centerline along the length of the second wiring pattern as a center point;
• generating at the intersection as a center a rectangular-shaped expansion region by expanding the rectangular-shaped overlapping region;
• generating a merge pattern by merging the second wiring pattern and the rectangular-shaped expansion region;
• and
• dividing the merge pattern into a plurality of regions along a single direction.

A semiconductor device, comprising:

• a substrate;
• a first interlayer insulating layer on the substrate;
• a first metal wiring on the first interlayer insulating layer, the first metal wiring having a width of W, extending in a first direction, and having a first end portion;
• a second interlayer insulating layer covering the first metal layer and the first interlayer insulating layer;
• a second metal wiring on the second interlayer insulating layer, the second metal wiring extending in a diagonal direction forming a predetermined angle with the first metal wiring, having a second end portion positioned above first end portion of the first metal wiring, and having a width wider than width W of the first metal wiring;
• a VIA contact passing through the second interlayer insulating layer and connecting the first end portion of the first metal wiring and the second end portion of the second metal wiring.

A computer readable recording medium, which is recorded with a program for causing an automated layout device to operate, the program comprising:

• generating a first wiring pattern with width W extending in a first direction;
• generating a second wiring pattern extending in a direction diagonal to the first wiring pattern so that the end portion thereof ends at the end portion of the first wiring pattern;
• detecting the intersection of a centerline along the length of the first wiring pattern and a centerline along the length of the second wiring pattern;
• and
• generating along the first wiring pattern with the extracted intersection as the center, a rectangular-shaped VIA pattern having an aspect ratio of at least two but no greater than five.

A computer readable recording medium, which is recorded with a program for causing an optical correction device to operate, the program comprising:

• reading out a wiring layout including a first wiring pattern, which extends in a first direction and is generated by an automated layout device;
• a second wiring pattern, which extends in a direction diagonal to the first wiring pattern and has an overlapping region where the end portion thereof and the end portion of the first wiring patter overlap;
• and a rectangular-shaped VIA pattern positioned at the overlapping region;
• generating an expanded region by expanding the rectangular-shaped VIA pattern a predetermined rate with the center point thereof as a reference;
• generating a merge pattern by merging the expanded region and the second wiring pattern;
• and
• dividing the merge pattern into a plurality of regions along a single direction.