Scan test circuit
AssigneeNEC Electronics Corporation
InventorShinji Kashiwagi
Life of this patent
Estimating the term…
Abstract
A scan test circuit (100) including a path for capturing a control signal during a test mode is disclosed. Scan test circuit (100) may include a control supply circuit (20), a clock control circuit (30), a control signal test circuit (40), and a scan flip-flop (1). Control supply circuit (20) may receive a control signal (Enable signal), which may be used for enabling a clock signal (CLK) in a gated clock system. A control supply test circuit (40) may provide a signal path that can apply control signal (Enable signal) to scan flip-flop (1) for capturing. In this way, functionality of a combination circuit used for generating a control signal (Enable signal) may be verified.
Claims20
A scan test circuit, comprising:
- a control signal test circuit coupled to receive a control signal having a control signal logic level and provide a control test circuit output based on the control signal logic level to a scan flip-flop during a control test mode of operation.
A scan test circuit, comprising:
- a scan flip-flop coupled to receive scan data in a scan chain at a scan data input terminal and a control signal test circuit output at a data input terminal;
- a clock control circuit coupled to receive a control signal and provide a clock signal to a clock input terminal of the scan flip-flop;
- and
- a control signal test circuit coupled to receive the control signal and a first data from a combination circuit and provide the control signal test circuit output.
A scan test circuit, comprising:
- a scan flip-flop coupled to receive scan data in a scan chain at a scan data input terminal and a control signal test circuit output at a data input terminal;
- a control supply circuit coupled to receive a control signal from a combination circuit and provide a control supply output;
- a clock control circuit coupled to receive the control supply output and provide a clock signal to a clock input terminal of the scan flip-flop;
- and
- a control signal test circuit coupled to receive the control signal and the first data from the combination circuit and provide the control signal test circuit output.
Dependencies are inferred from the claim text.