Integrated circuit facilitating its unit test
OwnerMakoto Hatakenaka, Atsuo Mangyo +1inventors
InventorsMakoto Hatakenaka, Atsuo Mangyo, Manabu Miura
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Abstract
An integrated circuit is provided that can achieve the unit test of its memory simply and positively. It makes a decision as to whether a memory is normal or not according to a 1-bit identity decision result output from an identity/nonidentity decision circuit. It obviates the need for assigning a plurality of decision terminals to each chip to be tested, making it possible to simultaneously test the same number of chips as the total number of the decision terminals of a tester, which is physically limited. It can improve test efficiency and reduce test cost.
Claims8
An integrated circuit comprising:
- test data write means for writing m×n-bit test data into a memory to be tested, in a single write operation by supplying same m-bit test data to each of n m-bit data buses that constitute an m×n-bit wide data bus connecting said test data write means to the memory to be tested;
- and
- decision means for receiving m×n-bit test data read out of the memory onto the wide data bus on an m-bit by m-bit basis in parallel, for comparing each m-bit test data with a same expected value of the m-bit test data every time the m-bit test data is supplied to said decision means, and for making a decision that the memory is normal only when all the m-bit test data supplied to the decision means agree with the expected value.
Dependencies are inferred from the claim text.