Trace circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKazuaki Kurooka, Teruaki Kanzaki
Life of this patent
Estimating the term…
Abstract
The trace circuit comprises the event control circuit and tow trace buffer memories. The event control circuit receives data on the control bus, address bus, and data bus and makes the data stored cyclically and alternately in the two buffer memories. Also, the event control circuit makes the two buffer memories output the store data cyclically and alternately.
Claims10
A trace circuit built-in a debugging circuit that is in turn built-in a microcomputer and performs program debugging, said trace circuit tracing data on a bus of said microcomputer according to a bus clock signal and outputting the result to an emulator, said trace circuit comprising:
- plural trace buffer memories in which the data on said bus of said microcomputer is stored according to the bus clock signal;
- and
- a control circuit which makes said trace buffer memories store cyclically and in a predetermined order the data on said bus, makes said trace buffer memories output cyclically and in a predetermined order the stored data, wherein the storage of data in and output of data from said trace buffer memories is performed in synchronization with the bus clock signal;
- and
- an output terminal through which the data stored in said trace buffer memories is output to said emulator.
A trace circuit built-in a debugging circuit that is in turn built-in a microcomputer and performs program debugging, said trace circuit tracing data on a bus of said microcomputer according to a bus clock signal and outputting the result to an emulator, said trace circuit comprising:
- two trace buffer memories in which the data on said bus of said microcomputer is stored according to the bus clock signal;
- and
- a control circuit which makes said trace buffer memories store cyclically and alternately the data on said bus, makes said trace buffer memories output cyclically and alternately the stored data, wherein the storage of data in and output of data from said trace buffer memories is performed in synchronization with the bus clock signal;
- and
- an output terminal through which the data stored in said trace buffer memories is output to said emulator.
Dependencies are inferred from the claim text.