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US 2002/0162042 A1Published application
Clock multiplier selection for a microprocessor with multiple system bus clocking frequencies
AssigneeIntel Corporation
InventorsFloyd Goodrich III, Shannon J. Poulin
Life of this patent
Estimating the term…
Abstract
Clock multiplier selection methods and apparatuses. One embodiment includes a clock interface to receive a clock signal, a frequency detect circuit, and a multiplier selection circuit. The frequency detect circuit detects an operating frequency of the clock signal and the multiplier selection circuit selects a clock multiplier that is a function of the operating frequency of the clock signal.
Claims24
An apparatus comprising:
- a clock interface to receive a clock signal;
- a frequency detect circuit to detect an operating frequency of the clock signal;
- a multiplier selection circuit to select a clock multiplier that is a function of the operating frequency of the clock signal.
A system comprising:
- a system clock that operates at a system clock frequency;
- system logic to generate a system clock frequency indicator to indicate the system clock frequency;
- a frequency detect circuit to detect the system clock frequency;
- a multiplier selection circuit to select a clock multiplier as a function of the system clock frequency.
1 more element
An electronic component comprising:
- a clock input to receive a clock operating at a clock frequency;
- a clock multiplied portion that operates at an operating frequency that is a multiple of said clock frequency;
- a multiplier selection circuit to select a either first multiplier if said clock frequency is approximately a first clock frequency or a second multiplier if a second clock frequency is received.
A method comprising:
- detecting a received clock frequency;
- selecting a clock multiplier as a function of said received clock frequency.
A microprocessor comprising:
- a clock interface to receive an external clock signal having an external clock signal frequency;
- a clock circuit to receive said external clock signal and to generate therefrom an internal clock signal that operates at an internal clock signal frequency which is a multiple of the external clock signal frequency;
- a clock multiplied portion to operate at the internal clock signal frequency;
- a clock multiplier selection circuit to select one of a plurality of N clock multipliers as the multiple depending on the external clock signal frequency.
1 more element
Dependencies are inferred from the claim text.