Scan-based state save and restore method and system for inactive state power reduction
OwnerPaul Richard Woods, Jay Dean McDougalinventors
Life of this patent
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Abstract
A scan-based state save and restore method and system for inactive state power reduction. An integrated circuit that has an inactive state has normal circuitry and scan circuitry. Upon receipt of a sleep signal, the state of the normal circuitry is accessed by employing scan circuitry. The state is then stored in a memory. The power is disconnected from the normal circuitry. Upon wake-up, the normal circuitry is re-connected to the power. The state of the circuit is accessed from the memory and restored to the normal circuitry by employing scan circuitry.
Claims20
A circuit having scan circuitry comprising:
- a) a constant power area that receives constant power;
- b) a switched power area that receives interruptible power;
- and
- c) an inactive state power reduction manager disposed in the constant power area for receiving a sleep signal and responsive thereto for asserting a stop clock signal to stop a normal mode clock, for performing a scan-based state-save, and for asserting a power control signal that is used to disconnect the switched power area from a power supply pad;
- and for receiving a wake up signal, and responsive thereto for de-asserting the power control signal that is used to connect the switched power area to the power supply pad, for performing a scan-based state restore, and for de-asserting the stop clock signal to resume the normal mode clock.
A method for inactive state power reduction for a circuit that has scan circuitry and a switched power portion comprising:
- a) receiving a sleep signal;
- responsive to the sleep signal,
- b) stopping a normal mode clock;
- c) performing a state save by employing the scan circuitry;
- d) disconnecting the switched power portion of the circuit from power;
- e) receiving a wake-up signal;
- responsive to the wake-up signal,
- f) re-connecting the switched power portion of the circuit to power;
- g) performing a state restore by employing the scan circuitry;
- and
- h) re-starting the normal mode clock.
A circuit board comprising:
- a) a first integrated circuit having a test access port;
- b) a second integrated circuit having a test access port;
- and
- c) an inactive state power reduction manager coupled to the first integrated circuit and the second integrated circuit for receiving a sleep signal and responsive thereto for asserting a stop clock signal to stop a normal mode clock, for performing a scan-based state save of state information of the first integrated circuit and the second integrated circuit, and for asserting a power control signal that is used to disconnect the first integrated circuit and the second integrated circuit from a power supply;
- and for receiving a wake up signal, and responsive thereto for de-asserting the power control signal that is used to re-connect the first integrated circuit and the second integrated circuit to the power supply, for performing a scan-based state restore for restoring state information to the first integrated circuit and the second integrated circuit, and for de-asserting the stop clock signal to resume the normal mode clock.
Dependencies are inferred from the claim text.