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US 2002/0161992 A1Published application
Processor and reset control method for the processor
AssigneeFujitsu Limited
InventorsHiroyuki Utsumi, Taizoh Satoh
Life of this patent
Estimating the term…
Abstract
The processor includes the first through third areas which can be initialized based on an input of the PRST signal. The second and third areas can be initialized based on an input of the HRST signal. The third area can be initialized based on an input of the SRST signal. The first area is not initialized if the second reset signal is generated. The first and second areas are not initialized if the third reset signal is generated. When initialization is to performed, the values of the flags corresponding to each area are referred to. Only those areas whose values of the flags have been reset are initialized.
Claims11
A processor comprising:
- a first initial setting area which is initialized based on an input of a first reset signal;
- a second initial setting area which is initialized based on an input of either the first reset signal or a second reset signal and which do not overlap with said first initial setting area;
- a first flag that is cleared by an input of the first reset signal and that is set when initial setting of the first initial setting area has been completed;
- and
- a second flag that is cleared by an input of either the first or second reset signals and that is set when initial setting of the second initial setting area has been completed, wherein
- when either one of the first and second reset signals is input, initial setting area/s corresponding to cleared flag/s is/are initialized out of the first and second initial setting areas.
3 more elements
A method of controlling resetting of a processor, the processor including
- a first initial setting area which is initialized based on an input of a first reset signal;
- a second initial setting area which is initialized based on an input of either the first reset signal or a second reset signal and which do not overlap with said first initial setting area;
- a first flag that is cleared by an input of the first reset signal and that is set when initial setting of the first initial setting area has been completed;
- and
- a second flag that is cleared by an input of either the first or second reset signals and that is set when initial setting of the second initial setting area has been completed, wherein
- when either one of the first and second reset signals is input, initial setting area/s corresponding to cleared flag/s is/are initialized out of the first and second initial setting areas,
- the method comprising:
- the step in which flags that correspond to each reset signal type are cleared;
- the step in which a state of each flag is confirmed, initial setting is performed for an initial setting area corresponding to the cleared flags and, after the initial setting is completed, setting corresponding flags is repeatedly performed until all of the flags are placed in a set state.
6 more elements
A method of controlling resetting of a processor, the processor including
- a first initial setting area which is initialized based on an input of a first reset signal;
- a second initial setting area which is initialized based on an input of either the first reset signal or a second reset signal and which do not overlap with said first initial setting area;
- a first flag that is cleared by an input of the first reset signal and that is set when initial setting of the first initial setting area has been completed;
- and
- a second flag that is cleared by an input of either the first or second reset signals and that is set when initial setting of the second initial setting area has been completed, wherein
- when either one of the first and second reset signals is input, initial setting area/s corresponding to cleared flag/s is/are initialized out of the first and second initial setting areas,
- the method comprising the steps of:
- clearing the first flag if the first reset signal is received, and clearing the first and second flags if the second reset signal is received;
- checking which flag/s has/have been cleared out of the first and second flags;
- initializing initial setting area/s corresponding to the cleared flag/s out of the first and second areas, and
- setting flag/s corresponding to the initial setting area/s which has/have been initialized out of the first and second areas.
8 more elements
A method of controlling resetting of a processor, the processor including
- a first initial setting area which is initialized based on an input of a first reset signal;
- a second initial setting area which is initialized based on an input of either the first reset signal or a second reset signal and which do not overlap with said first initial setting area;
- a third initial setting area which is initialized based on an input of the first or second reset signals or a third input signal and which do not overlap with both said first initial setting area and said second initial setting area;
- a first flag that is cleared by an input of the first reset signal and that is set when initial setting of the first initial setting area has been completed;
- a second flag that is cleared by an input of either the first or second reset signals and that is set when initial setting of the second initial setting area has been completed, and
- a third flag that is cleared by an input of any one of the first through third reset signals and that is set when initial setting of the third initial setting area has been completed, wherein
- when any one of the first through third reset signals is input, initial setting area/s corresponding to cleared flag/s is/are initialized out of the first through third initial setting areas,
- the method comprising the steps of:
- clearing the first flag if the first reset signal is received, clearing the first and second flags if the second reset signal is received, and clearing the first through third flags if the third reset signal is received;
- checking which flag/s has/have been cleared out of the first through third flags;
- initializing initial setting area/s corresponding to the cleared flag/s out of the first through third areas, and
- setting flag/s corresponding to the initial setting area/s which has/have been initialized out of the first through third areas.
9 more elements
A method of controlling resetting of a processor, the processor including
- a first initial setting area which is initialized based on an input of a first reset signal;
- a second initial setting area which is initialized based on an input of either the first reset signal or a second reset signal and which do not overlap with said first initial setting area;
- a third initial setting area which is initialized based on an input of the first or second reset signals or a third input signal and which do not overlap with both said first initial setting area and said second initial setting area;
- an n-th initial setting area, where n is an integer having value equal to or more than 4, which do not overlap with each initial setting area from the first initial setting area through an (n−1) -th initial setting area and which is initialized based on an input of the first reset signal through an n-th reset signal different from any of the first through an (n−1)-th reset signal;
- a first flag that is cleared by an input of the first reset signal and that is set when initial setting of the first initial setting area has been completed;
- a second flag that is cleared by an input of either the first or second reset signals and that is set when initial setting of the second initial setting area has been completed;
- a third flag that is cleared by an input of any one of the first through third reset signals and that is set when initial setting of the third initial setting area has been completed, and
- an n-th flag that is cleared by an input of any of the first reset signal through the n-th reset signal and that is set when initial setting of the n-th initial setting area has been completed, wherein
- when any one of the first through n-th reset signals is input, initial setting area/s corresponding to cleared flag/s is/are initialized out of the first through n-th initial setting areas,
- the method comprising the steps of:
- clearing the first flag if the first reset signal is received, clearing the first and second flags if the second reset signal is received, clearing the first through third flags if the third reset signal is received, and clearing the first through n-th flags if the n-th reset signal is received;
- checking which flag/s has/have been cleared out of the first through n-th flags;
- initializing initial setting area/s corresponding to the cleared flag/s out of the first through n-th areas, and
- setting flag/s corresponding to the initial setting area/s which has/have been initialized out of the first through n-th areas.
11 more elements
Dependencies are inferred from the claim text.