System and method including distributed instruction buffers holding a second instruction form

A processor for processing a first instruction form and a second instruction form of an instruction set comprising:

• a plurality of execution units for receiving instructions;
• a branch unit connected to an instruction fetch unit for the first instruction form and a sequencer for the second instruction form;
• a decode unit for decoding instructions of the first instruction form into control signals for the execution units;
• and
• a plurality of buffers, proximate to the execution units, for storing predecoded instructions of the second instruction form.

A processor for processing a first instruction form and a second instruction form of an instruction set comprising:

• a plurality of execution units for receiving instructions;
• a branch unit connected to an instruction fetch unit for the first instruction form and a sequencer for the second instruction form, wherein the branch unit switches the processor from the first instruction form to the second instruction form in response to a branch instruction of the first instruction form and switches the processor from the second instruction form to the first instruction form in response to a branch instruction of the second instruction form;
• a decode unit adapted to decode instructions of the first instruction form into instructions for the execution units;
• an issue unit adapted to sequence decoded instructions of the first instruction form;
• a plurality of buffers, proximate to the execution units, adapted to storing predecoded instructions of the second instruction form, wherein each execution unit is connected to a buffer;
• a compiler adapted for generating instructions of the first form and instructions of the second form based on execution frequency, wherein instructions of the second form are executed more frequently than instructions of the first form;
• and
• the sequencer, engaged by the branch unit, adapted to fetch the predecoded instructions and sequence the predecoded instruction of the second instruction form, wherein the sequencer is connected to a plurality of gates connected between a plurality of execution queues adapted to store the decoded instructions of the first instruction form and the plurality of execution units, the sequencer further adapted to control the gates.