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US 2002/0161986 A1Published application
Instruction processing method for verifying basic instruction arrangement in VLIW instruction for variable length VLIW processor
AssigneeFujitsu Limited
InventorsTeruhiko Kamigata, Hideo Miyake
Life of this patent
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Abstract
An instruction processing method for checking an arrangement of basic instructions in a very long instruction word (VLIW) instruction, suitable for language processing systems, an assembler and a compiler, used for processors which execute variable length VLIW instructions designed based on variable length VLIW architecture.
Claims12
A method for instruction processing, comprising:
- a first step of identifying a classification of a functional unit which can execute a basic instruction;
- a second step of determining whether said basic instruction can be assigned to a logical instruction slot through checking a relationship between said classification of said functional unit and said logical instruction slot;
- and
- a third step of assigning, to an instruction slot, said basic instruction determined to be assignable to said logical instruction slot.
1 more element
A computer program, comprising:
- a first step of identifying a classification of a functional unit which can execute a basic instruction;
- a second step of determining whether said basic instruction can be assigned to a logical instruction slot through checking a relationship between said classification of said functional unit and said logical instruction slot;
- and
- a third step of assigning, to an instruction slot, said basic instruction determined to be assignable to said logical instruction slot.
1 more element
Dependencies are inferred from the claim text.