US 2002/0161979 A1 · Speculative dram reads with cancel data mechanism

Abstract

Disclosed is a method and memory subsystem that allows for speculative issuance of reads to a DRAM array to provide efficient utilization of the data out bus and faster read response for accesses to a single DRAM array. Two read requests are issued simultaneously to a first and second DRAM in the memory subsystem, respectively. Data issued from the first DRAM is immediately placed on the data out bus, while data issued from the second DRAM is held in an associated buffer. The processor or memory controller then generates a release signal if the second read is not speculative or is correctly speculated. The release signal is sent to the second DRAM after the first issued data is placed on the bus. The release signal releases the data issued from the second DRAM to the buffer from the buffer on to the data out bus. Because the data has already been issued when the release signal is received, no loss of time is incurred in issuing the data from the DRAM and only a small clock cycle delay occurs between the first issued data and the second issued data on the data out bus.

Claims33

Dependent claims

A memory subsystem comprising:

a memory controller;
a memory device coupled to said memory controller comprising at least a first memory component and a second memory component, wherein each of said first and second memory components are coupled to said memory controller via individual address buses;
a shared data bus coupled to each of said first and second memory components;
a buffer associated with at least said second memory component;
and
logic associated with said memory controller and buffer that controls an issuance of first data and second data from said first and said second memory component, respectively, wherein when said second data are issued at a time when said second data would overlap with said first data on said shared data bus, said second data is held in said buffer, while said first data is forwarded to said shared data bus.

3 more elements

Dependencies are inferred from the claim text.

Speculative dram reads with cancel data mechanism

Life of this patent

Speculative dram reads with cancel data mechanism

Life of this patent

Abstract

Claims33