Multi-service system-on-chip including on-chip memory with multiple access path
OwnerGeorge Apostol JR., Jeffrey S. Earlinventors
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Abstract
In an integrated circuit, a memory unit includes a first and a second data transfer interface. The first data interface services successive first accesses by a processor and subsystem of the IC, whereas the second data interface services second accesses by at least the processor in parallel. In one embodiment, the accesses are properly sequenced and responded to.
Claims38
A memory unitfor use in an integrated circuit (IC) comprising:
- an array of memory cells;
- a first data transfer interface coupled to the array of memory cells to provide a first access path for a selected one of a processor and a plurality of subsystems of the IC to access said array of memory cells;
- a second data transfer interface coupled to the array of memory cells to provide a second access path for said processor to access said array of memory cells;
- and
- a controller coupled to the array of memory cells and the first and second data transfer interfaces to control said array of memory cells and said first and second data transfer interfaces to facilitate concurrent accesses of said memory unit by said processor and said subsystems.
In a memory unit of an integrated circuit (IC), a method of operation comprising:
- queuing first memory accesses of a processor and a plurality of subsystems of the IC in inbound queues of a first data transfer interface;
- queuing second memory accesses of the processor in an inbound queue of a second data transfer interface;
- sequencing said first and second memory accesses into a single sequence of memory accesses;
- and
- servicing said first and second memory accesses in accordance with their sequence order.
An integrated circuit comprising:
- a processor;
- a plurality of subsystems;
- and
- a memory unit coupled to said processor and said subsystems having at least a first access path to facilitate access by a selected one of said processor and said subsystem to access said memory unit and a second access path to facilitate access by said processor.
In an integrated circuit (IC), a method of operation comprising:
- a processor and a plurality of subsystem of the IC successively making first memory accesses of a memory unit of the IC via a first access path in turn;
- the processor also successively making second memory accesses to said memory unit via a second access path in parallel;
- and
- the memory unit servicing said first and second memory accesses made through said first and second access paths in parallel.
The method of claim 38, wherein the method further comprises
- said processor making a second access of said memory unit via said first access path, and awaiting for a second reply to said second access of said memory unit;
- and
- said processor making said first access of said memory unit via said second access path for said first data placed into said memory unit by said first subsystem after also receiving said second reply for said second access of said memory unit.
Dependencies are inferred from the claim text.