US 2002/0161976 A1 · Data processor

Abstract

The data processor has a set-associative cache memory capable of performing associative operation using tag information for an indexed cache line. The cache memory includes way prediction part for performing a selection of a way based on the prediction in parallel with the associative operation, generation part for generating way selection determining information based on the associative operation using the subsequent access address during a penalty cycle caused by a prediction miss of the way prediction part, and control part for making a way selected for the subsequent access address after the penalty cycle on the basis of the way selection determining information. Since a way to be hit at the subsequent cache access can be predetermined during the preceding penalty cycle, the cumulative number of penalty cycles can be reduced.

Claims16

Dependent claims

A data processing device including a set-associative cache memory capable of performing associative operation using tag information for an indexed cache line, said cache memory comprising:

way prediction means for performing way selection based on the prediction in parallel with the associative operation;
generation means for generating way selection determining information based on the associative operation using the subsequent access address during a penalty cycle caused by a prediction miss of said way prediction means;
and
control means for making a way selected for the subsequent access address after the penalty cycle on the basis of the way selection determining information.

1 more element

Dependencies are inferred from the claim text.

Data processor

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Data processor

Life of this patent

Abstract

Claims16