Memory system having stub bus configuration

A memory system having a stub configuration comprising:

• a controller for generating a first flag signal, a control signal, an address signal, and data signals on a data bus, the data bus, first flag signal, control signal, and address signal being arranged in a stub configuration;
• and
• a memory module including memory devices coupled to the controller, the memory module receiving the first flag signal and the control signal that includes a read or write command;
• the memory module, in response to the write command, initiating a write operation for writing the data signals from the data bus to the memory devices in response to the first flag signal;
• and
• the memory module, in response to the read command, initiating a read operation for reading data from the memory devices to the data bus in response to the first flag signal and generating a second flag signal in response to the first flag signal, the second flag signal being provided to the controller, the controller receiving the data signals on the data bus in response to the second flag signal during the read operation.

A memory system having a stub configuration comprising:

• a controller for generating a first clock signal, a control signal, an address signal and data signals on a data bus, the data bus, first clock signal, control signal, and address signal being arranged in a stub configuration;
• a second clock signal generator for generating a second clock signal;
• a memory module including memory devices coupled to the controller, the memory module receiving the first clock signal, the second clock signal and the control signal that includes a read or write command;
• the first clock signal propagating from the controller to the memory module in a first direction of propagation, and the second clock signal propagating from the memory module to the controller in a second direction of propagation;
• the memory module, in response to the write command, initiating a write operation for writing the data signals from the data bus to the memory devices in synchronization with the first clock signal;
• and
• the memory module, in response to the read command, initiating a read operation for reading data from the memory to the data bus in response to the second clock signal, the controller receiving the data signals on the data bus in response to the second clock signal during the read operation.

A memory system having a stub configuration comprising:

• a controller for generating a first clock signal, a control signal, an address signal, and data signals on a data bus, the data bus, first clock signal, control signal, and address signal being arranged in a stub configuration;
• and
• a memory module coupled to the controller, the memory module having first and second faces including memory devices on both first and second faces and including a control and address buffer on the first face, the memory module receiving the first clock signal, the address signal and the control signal that includes a read or write command;
• the memory module, in response to the write command, initiating a write operation for writing the data signals from the data bus to the memory devices in synchronization with the first clock signal;
• and
• the memory module, in response to the read command, initiating, at the control and address buffer, a read operation for reading data from the memory devices to the data bus in synchronization with the first clock signal and generating a second clock signal in response to the first clock signal, the second clock signal being provided to the controller, the controller receiving the data signals on the data bus in response to the second clock signal during the read operation.

A memory system having a stub configuration comprising:

• a controller for generating a first flag signal, a control signal, an address signal, and data signals on a data bus, the data bus, first flag signal, control signal, and address signal being arranged in a stub configuration;
• a memory module including memory devices coupled to the controller, the memory module receiving the first flag signal and the control signal that includes a read or write command;
• the memory module, in response to the write command, initiating a write operation for writing the data signals from the data bus to the memory devices in response to the first flag signal;
• and
• the memory module, in response to the read command, initiating a read operation for reading data from the memory devices to the data bus in response to the first flag signal and generating a second flag signal in response to the first flag signal, the second flag signal being provided to the controller, the controller receiving the data signals on the data bus in response to the second flag signal during the read operation;
• and
• a motherboard coupling the memory module and the controller, the motherboard including the data bus, a control bus for transfer of the control signal, an address bus for transfer of the address signal, a first flag signal line for transfer of the first flag signal, and a second flag signal line for transfer of the second flag signal, the first flag signal line and the second flag signal line being routed with the control and address buses.

A method of transferring data in a memory system having a stub configuration comprising:

• generating a first clock signal, a control signal, an address signal and data signals on a data bus at a controller, the data bus, first clock signal, control signal, and address signal being arranged in a stub configuration;
• and
• receiving the first clock signal and the control signal that includes a read or write command at a memory module including memory devices coupled to the controller,
• the memory module, in response to the write command, initiating a write operation for writing the data signals from the data bus to the memory devices in synchronization with the first clock signal;
• and
• the memory module, in response to the read command, initiating a read operation for reading data from the memory devices to the data bus in synchronization with the first clock signal and generating a second clock signal in response to the first clock signal, the second clock signal being provided to the controller, the controller receiving the data signals on the data bus in response to the second clock signal during the read operation.

A method of transferring data in a memory system having a stub configuration comprising:

• generating a first flag signal, a control signal, an address signal, and data signals on a data bus at a controller, the data bus, first flag signal, control signal, and address signal being arranged in a stub configuration;
• and
• receiving the first flag signal and the control signal that includes a read or write command at a memory module including memory devices coupled to the controller;
• the memory module, in response to the write command, initiating a write operation for writing the data signals from the data bus to the memory devices in response to the first flag signal;
• and
• the memory module, in response to the read command, initiating a read operation for reading data from the memory devices to the data bus in response to the first flag signal and generating a second flag signal in response to the first flag signal, the second flag signal being provided to the controller, the controller receiving the data signals on the data bus in response to the second flag signal during the read operation.

A method of transferring data in a memory system having a stub configuration comprising:

• generating a first clock signal, a control signal, an address signal and data signals on a data bus at a controller, the data bus, first clock signal, control signal, and address signal being arranged in a stub configuration;
• generating a second clock signal at a second clock signal generator;
• receiving the first clock signal, the second clock signal and the control signal that includes a read or write command at a memory module including memory devices coupled to the controller;
• transmitting the first clock signal from the controller to the memory module in a first direction of propagation, and transmitting the second clock signal from the memory module to the controller in a second direction of propagation;
• the memory module, in response to the write command, initiating a write operation for writing the data signals from the data bus to the memory devices in synchronization with the first clock signal;
• and
• the memory module, in response to the read command, initiating a read operation for reading data from the memory to the data bus in response to the second clock signal, the controller receiving the data signals on the data bus in response to the second clock signal during the read operation.