Destructive read architecture for dynamic random access memories

A method for scheduling a write back operation in a destructive read DRAM architecture including a plurality of DRAM arrays, the method comprising:

• receiving an operational command;
• determining whether said operational command is:
• a read command, said read command resulting in reading out data from an addressed DRAM array referenced therewith;
• or
• a write command, said write command resulting in writing data to an addressed DRAM array referenced therewith;
• and
• regardless of which said operational command is received, determining whether a write back operation is to be executed, said write back operation comprising writing data temporarily stored in a specific address within an SRAM.

A method for scheduling a write back operation in a destructive read DRAM architecture including a plurality of DRAM arrays, the method comprising:

• receiving an operational command;
• determining whether said operational command is:
• a read command, said read command resulting in reading out data from an addressed DRAM array referenced therewith;
• or
• a write command, said write command resulting in writing data to an addressed DRAM array referenced therewith;
• or
• a no operation command;
• regardless of which said operational command is received, executing a write back determination, said write back determination determining whether there is any temporarily stored data in an SRAM to be written back to one of the plurality of DRAM arrays;
• and
• if there is any temporarily stored data in the SRAM to be written back to one of the plurality of DRAM arrays, then selecting the oldest data stored within the SRAM for write back.

A dynamic random access memory (DRAM) structure, comprising:

• an individual memory cell, said memory cell capable of storing a bit of information therein;
• a bit line, removably coupled to said memory cell, said bit line further being initially precharged prior to an operational command received in connection with said memory cell;
• a signal line, removably coupled to said bit line, said signal line receiving a signal initially generated on said bit line, wherein said bit line is no longer precharged when said signal is initially generated thereon;
• and
• a data line, removably coupled to said signal line;
• wherein said signal line is capable of transmitting a data bit, read from said memory cell, to said data line, simultaneously to said bitline being precharged again.

A dynamic random access memory (DRAM) structure, comprising:

• a plurality of individual memory cells organized into rows and columns, each column of memory cells being coupled to a corresponding word line, and each row of memory cells being removably coupled to one bit line in a pair of complementary bit lines;
• an equalizer, said equalizer precharging said pair of complementary bit lines to an equal voltage value;
• a multiplexer, said multiplexer removably coupling a selected pair of bit lines to a pair of signal lines;
• and
• a data line, said data line capable transferring data from said selected pair of bit lines, through said pair of signal lines, to a temporary storage device.

A dynamic random access memory (DRAM) architecture, comprising:

• a plurality of DRAM arrays;
• a temporary memory storage device in communication with said plurality of DRAM arrays, said temporary memory storage device temporarily storing data to be read from and written to said plurality of DRAM arrays;
• and
• a scheduler, said scheduler determining when data stored within said temporary memory storage device is to be written back to said plurality of DRAM arrays.