US 2002/0161966 A1 · Dram with memory independent burst lengths for reads versus writes

Abstract

A method and system that enables independent burst lengths for reads and writes to a DRAM subsystem. Specifically, the method provides a mechanism by which read bursts may be longer than write bursts since there are statistically more reads than writes to the DRAM and only some beats of read data are modified and need to be re-written to memory. In the preferred embodiment, the differences in the burst length is controlled by an architected address tenure, i.e., a set of bits added to the read and write commands that specify the specific number of beats to read and/or write. The bits are set by the processor during generation of the read and write commands and prior to forwarding the commands to the memory controller for execution.

Claims15

Dependent claims

A memory subsystem comprising:

a memory controller;
a memory array coupled to said memory controller via a system bus;
means for providing independent read and write access to said memory array via an architected address tenure, wherein said write access comprises only a write operation and writes only those beats that have been modified from among a larger number of beats that were read.

Dependencies are inferred from the claim text.

Dram with memory independent burst lengths for reads versus writes

Life of this patent

Dram with memory independent burst lengths for reads versus writes

Life of this patent

Abstract

Claims15