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US 2002/0161965 A1Published application
Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus
AssigneeMicron Technology, Inc.
InventorKEVIN J. RYAN
Life of this patent
Estimating the term…
Abstract
A memory system having at least one memory subsystem and using a packet protocol communicated over a command and address bus and at least one data bus. The memory subsystems are pipelined to achieve wide data paths and to support a high number of memory devices, such as dynamic random access memory devices, per data bus. The packet protocol is defined to compensate for the delay stages of the pipelined memory subsystem in order to optimize the access time of the memory devices.
Claims31
A memory system comprising:
- a memory controller;
- a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;
- a bidirectional data bus coupled to the memory controller, the memory controller communicating data information to the bidirectional data bus for a write operation and receiving the data information from the bidirectional data bus during a read operation;
- a plurality M of memory devices;
- a buffer register connected between the command and address bus and the plurality of memory devices, the buffer register receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices;
- and
- a data register connected between the plurality of memory devices and the bidirectional data bus, the data register receiving and latching the data information from the bidirectional data bus and driving the data information to the plurality of memory devices for a write operation, the data register receiving and latching the data information from the plurality of memory devices and driving the data information to the bidirectional data bus for a read operation.
4 more elements
A memory system comprising:
- a memory controller;
- a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;
- a bidirectional data bus coupled to the memory controller, the memory controller communicating data information to the bidirectional data bus for a write operation and receiving the data information from the bidirectional data bus during a read operation;
- and
- a plurality N of pipelined memory subsystems, wherein each memory subsystem includes:
- a) a plurality M of memory devices;
- b) a buffer register connected between the command and address bus and the plurality of memory devices, the buffer register receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices;
- and
- c) a data register connected between the plurality of memory devices and the bidirectional data bus, the data register receiving and latching the data information from the bidirectional data bus and driving the data information to the plurality of memory devices for a write operation, the data register receiving and latching the data information from the plurality of memory devices and driving the data information to the bidirectional data bus for a read operation.
6 more elements
A memory system comprising:
- a memory controller;
- a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;
- a first bidirectional data bus coupled to the memory controller, the memory controller communicating first data information to the bidirectional data bus for a write operation and receiving the first data information from the bidirectional data bus during a read operation;
- a second bidirectional data bus coupled to the memory controller, the memory controller communicating second data information to the second bidirectional data bus for a write operation and receiving the second data information from the second bidirectional data bus during a read operation;
- a first plurality N of pipelined memory subsystems, wherein each memory subsystem includes:
- a plurality of memory devices;
- a buffer register connected between the command and address bus and the plurality of memory devices, the buffer register receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices;
- and
- a data register connected between the plurality of memory devices and the first bidirectional data bus, the data register receiving and latching the first data information from the first bidirectional data bus and driving the first data information to the plurality of memory devices for a write operation, the data register receiving and latching the first data information from the plurality of memory devices and driving the first data information to the first bidirectional data bus for a read operation;
- and
- a second plurality P of pipelined memory subsystems, wherein each memory subsystem includes:
- a plurality of memory devices;
- a buffer register connected between the command and address bus and the plurality of memory devices, the buffer register receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices;
- and
- a data register connected between the plurality of memory devices and the second bidirectional data bus, the data register receiving and latching the second data information from the second bidirectional data bus and driving the second data information to the plurality of memory devices for a write operation, the data register receiving and latching the second data information from the plurality of memory devices and driving the second data information to the bidirectional data bus for a read operation.
12 more elements
A memory system comprising:
- a memory controller;
- a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;
- a bidirectional data bus coupled to the memory controller, the memory controller communicating data information to the bidirectional data bus for a write operation and receiving the data information from the bidirectional data bus during a read operation;
- a memory module wherein each pipelined memory subsystem includes:
- a plurality M of memory devices;
- a buffer register connected between the command and address bus and the plurality of memory devices, the buffer register receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices;
- and
- a data register connected between the plurality of memory devices and the bidirectional data bus, the data register receiving and latching the data information from the bidirectional data bus and driving the data information to the plurality of memory devices for a write operation, the data register receiving and latching the data information from the plurality of memory devices and driving the data information to the bidirectional data bus for a read operation;
- and
- a socket adapted to receive the memory module and to couple the memory module to the unidirectional command and address bus and to the bidirectional data bus.
7 more elements
A memory system comprising:
- a memory controller;
- a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;
- a bidirectional data bus coupled to the memory controller, the memory controller communicating data information to the bidirectional data bus for a write operation and receiving the data information from the bidirectional data bus during a read operation;
- a plurality R of memory modules wherein at each memory module includes a plurality N of pipelined memory subsystems including:
- a plurality of memory devices;
- a buffer register connected between the command and address bus and the plurality of memory devices, the buffer register receiving and latching the commands and addresses from the command and address bus and driving the commands and addresses to the plurality of memory devices;
- a data register connected between the plurality of memory devices and the bidirectional data bus, the data register receiving and latching the data information from the bidirectional data bus and driving the data information to the plurality of memory devices for a write operation, the data register receiving and latching the data information from the plurality of memory devices and driving the data information to the bidirectional data bus for a read operation;
- and
- a plurality of sockets, wherein each socket is adapted to receive one of the R memory modules and to couple the received memory module to the unidirectional command and address bus and to the bidirectional data bus.
6 more elements
A memory system comprising:
- a memory controller;
- a unidirectional command and address bus coupled to the memory controller, the memory controller communicating commands and addresses to the command and address bus;
- a first bidirectional data bus coupled to the memory controller, the memory controller communicating first data information to the bidirectional data bus for a write operation and receiving the first data information from the bidirectional data bus during a read operation;
- a second bidirectional data bus coupled to the memory controller, the memory controller communicating second data information to the second bidirectional data bus for a write operation and receiving the second data information from the second bidirectional data bus during a read operation;
- a first and second memory module, the first and second memory module each having a first memory subsystem and a second memory subsystem;
- and
- a first and second socket, the first socket adapted to receive the first memory module and to couple the first memory module to the unidirectional command and address bus and to the first bidirectional data bus, the second socket adapted to receive the second memory module and to couple the second memory module to the unidirectional command and address bus and to the second bidirectional data bus.
4 more elements
A method for storing data in a pipelined memory system, comprising the steps of:
- communicating commands and addresses to a unidirectional command and address bus;
- communicating data information to a bidirectional data bus;
- latching the commands and addresses in a plurality of buffer registers;
- latching the data in a plurality of data registers;
- driving the latched commands and addresses to a plurality of memory devices having addressable storage;
- driving the latched data to the plurality of memory devices;
- and
- storing the data in the addressable storage of one of the plurality of memory devices.
5 more elements
A method for retrieving data in a pipelined memory system, comprising the steps of:
- issuing commands and addresses on a unidirectional command and address bus;
- latching the commands and addresses in a plurality of buffer registers;
- driving the latched commands and addresses to a plurality of memory devices having addressable storage;
- retrieving the data from the addressable storage of one of the plurality of memory devices;
- latching the data in a data register;
- and
- receiving the data on a bidirectional data bus.
4 more elements
Dependencies are inferred from the claim text.