Memory control device and LSI

A memory control device for arbitrating memory access contention among a plurality of bus masters accessing separate memory areas within a memory by selectively granting a bus use right that permits the usage of a memory bus to one of the plurality of bus masters at a time, the memory control device comprising:

• holding means for holding transfer rate information regarding each of the plurality of the bus masters, the transfer rate information indicating (i) a transfer rate at which a corresponding bus master performs data transfer to or from the memory, and (ii) an ensuring time period within which data transfer at the transfer rate is to be ensured;
• reference period calculating means for determining, as a reference time period, a time period equal to or shorter than a shortest ensuring time period among all the ensuring time periods;
• bus use permission time period calculating means for calculating bus use permission time periods, each of which is a time period that a bus master takes to transfer an amount of data V using a bus bandwidth of the memory bus, wherein V represents an amount of data that a corresponding bus master is capable of transferring at a corresponding transfer rate within the reference time period;
• and
• use right granting means for granting the bus use right to each bus master for a corresponding bus use permission time period within each reference time period that repeats cyclically.

An LSI including (i) a plurality of circuits that share a memory and (ii) a memory control device for arbitrating memory access contention by selectively granting a bus use right that permits the usage a memory bus to one of the plurality of circuits at a time, each circuit is required to perform data transfer to or from the memory at a fixed transfer rate, the memory control device comprising:

• holding means for holding transfer rate information regarding each of the plurality of the circuits, the transfer rate information indicating (i) a transfer rate at which a corresponding circuit performs data transfer to or from the memory, and (ii) an ensuring time period within which data transfer at the transfer rate is to be ensured;
• reference period calculating means for determining, as a reference time period, a time period equal to or shorter than a shortest ensuring time period among all the ensuring time periods;
• bus use permission time period calculating means for calculating bus use permission time periods, each of which is a time period that a circuit takes to transfer an amount of data V using a bus bandwidth of the memory bus, wherein V represents an amount of data that a corresponding circuit is capable of transferring at a corresponding transfer rate within the reference time period;
• and
• use right granting means for granting the bus use right to each circuit for a corresponding bus use permission time period within each reference time period that repeats cyclically.