Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation

An integrated circuit data comprising:

• 1) N bus devices capable of transferring data with one another;
• and
• 2) a bus interface unit for transferring data between said N bus devices, said bus interface unit comprising:
• a) N bus interfaces, each of said N bus interfaces comprising:
• i) an incoming request bus for receiving request packets from one of said N bus devices;
• ii) an outgoing request bus for transmitting request packets to said one of said N bus devices;
• iii) an incoming data bus for receiving data packets from said one of said N bus devices;
• and iv) an outgoing data bus for transmitting data packets to said one of said N bus devices;
• and
• b) an arbitration circuit capable of determining a first priority level associated with a first request packet received from a first bus device and capable of determining a second priority level associated with a second request packet received from a second bus device.

For use in a bus interface unit comprising N bus interfaces, each of the N bus interfaces comprising:

• i) an incoming request bus for receiving request packets from a corresponding one of N bus devices;
• ii) an outgoing request bus for transmitting request packets to the corresponding bus device;
• iii) an incoming data bus for receiving data packets from the corresponding bus device;
• and iv) an outgoing data bus for transmitting data packets to the corresponding bus device, a method of arbitrating requests received from the N bus interfaces, the method comprising the steps of:
• determining a first priority level associated with a first request packet received from a first bus device;
• determining a second priority level associated with a second request packet received from a second bus device;
• and
• comparing the first priority level and the second priority level to determine which of the first and second priority levels is higher.