Communication system for raising channel utilization rate and communication method thereof

A communication method performed in a communication system, which includes a CPU which stores information on packet data received/transmitted via a plurality of communication channels in each buffer descriptor and includes a DMA controller which stores packet data received via the plurality of communication channels in a memory or transmits packet data stored in the memory via the plurality of communication channels, the communication method comprising:

• (a) displaying a current status of a buffer descriptor using a flag bit, wherein the flag bit is allotted to the buffer descriptor by the CPU;
• (b) determining whether the CPU is organizing a buffer descriptor to be processed by the DMA controller, whether error occurred in the packet data transmitted via the communication channels, or whether the DMA controller is accessible after the organization of the buffer descriptor is completed, by using the DMA controller to identify the flag bit;
• (c) continuously identifying the flag bit using the DMA controller until the organization of the buffer descriptor to be accessed is completed if the CPU is organizing the buffer descriptor to be accessed in step (b);
• (d) skipping the buffer descriptor currently being accessed if it is determined that error occurred in the communication channels in step (b), and performing step (b) again to process the next buffer descriptor;
• (e) processing packet data whose information is stored in the buffer descriptor currently being accessed if the buffer descriptor currently being accessed is in a DMA mode, in which the DMA controller can access the buffer descriptor, in step (b);
• and
• (f) converting the buffer descriptor processed in step (e) from the DMA mode into a CPU mode in which the CPU can access the buffer descriptor, and moving to a buffer descriptor to be processed next.

A buffer descriptor for storing packet data information comprising:

• an ownership bit for indicating that the buffer descriptor is in a central processing unit (CPU) mode the buffer descriptor is being organized or an error occurred in packet data, and for indicating that the buffer descriptor is in a direct memory access (DMA) mode, in which a DMA controller is accessible, if the organization of the buffer descriptors is completed;
• a skip bit for indicating whether a CPU is organizing the buffer descriptor or whether an error occurred in packet data received via a communication channel;
• a status bit for indicating a status after a communication system transmits/receives packet data;
• a data pointer for indicating an address in a memory in which packet data is stored or the address in the memory at which packet data to be transmitted through the communication channel is recorded;
• and
• a command bit for indicating a packet data processing command.