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US 2002/0161807 A1Published application
Two-dimensional pyramid filter architecture
AssigneeIntel Corporation
InventorTinku Acharya
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Abstract
Embodiments of a two-dimensional pyramid filter architecture are described.
Claims23
An integrated circuit comprising:
- a two-dimensional pyramid filter architecture of an order 2N−1, where N is a positive integer greater than three;
- said two dimensional pyramid filter architecture of order 2N−1, in operation, capable of producing, on respective clock cycles, at least the following:
- pyramid filtered output signals corresponding to output signals produced by four one-dimensional pyramid filters of order 2N−1;
- and
- pyramid filtered output signals corresponding to output signals produced either by four two-dimensional pyramid filters or one two-dimensional pyramid filter of order [2(N−1)−1] using signal sample matrices of order [2(N−1)−1];
- wherein the respective output signals in said two dimensional pyramid filter architecture are summed on respective clock cycles of said two dimensional pyramid filter architecture.
3 more elements
A method of filtering an image using a two-dimensional pyramid filter architecture of order 2N−1, where N is a positive integer greater than three, said method comprising:
- summing, on respective clock cycles of said two dimensional pyramid filter architecture, the following:
- pyramid filtered output signals corresponding to output signals produced by four one-dimensional pyramid filters of order 2N−1;
- and
- pyramid filtered output signals corresponding to output signals produced either by four two-dimensional pyramid filters or one two-dimensional pyramid filter of order [2(N−1)−1] using signal sample matrices of order [2(N−1)−1].
1 more element
An article comprising:
- a storage medium, said storage medium having stored thereon instructions, that, when executed result in filtering an image using a two-dimensional pyramid filter architecture of order 2N−1, where N is a positive integer greater than three, by:
- summing, on respective clock cycles of said two dimensional pyramid filter architecture, the following:
- pyramid filtered output signals corresponding to output signals produced by four one-dimensional pyramid filters of order 2N−1;
- and
- pyramid filtered output signals corresponding to output signals produced either by four two-dimensional pyramid filters or one two-dimensional pyramid filter of order [2(N−1)−1] using signal sample matrices of order [2(N−1)−1].
2 more elements
An image processing system comprising:
- an image processing unit to filter scanned color images;
- said image processing unit including at least one two-dimensional pyramid filter architecture;
- said at least one two-dimensional pyramid filter architecture comprising:
- a two-dimensional pyramid filter architecture of an order 2N−1, where N is a positive integer greater than three;
- said two dimensional pyramid filter architecture of order 2N−1, in operation, capable of producing, on respective clock cycles, at least the following:
- pyramid filtered output signals corresponding to output signals produced by four one-dimensional pyramid filters of order 2N−1;
- and
- pyramid filtered output signals corresponding to output signals produced either by four two-dimensional pyramid filters or one two-dimensional pyramid filter of order [2(N−1)−1] using signal sample matrices of order [2(N−1)−1];
- wherein the respective output signals in said two dimensional pyramid filter architecture are summed on respective clock cycles of said two dimensional pyramid filter architecture.
6 more elements
Dependencies are inferred from the claim text.