State machine, semiconductor device using state machine, and method of design thereof

Abstract

A flexible and reliable state machine and a semiconductor device using the state machine are provided. A state machine includes a memory circuit (1), a comparator circuit (2), an analyzer circuit (3) and an arithmetic circuit (4). The memory circuit (1) receives and holds data (5-1a) indicative of the next state, and outputs it as data (5-1b) indicative of present state. The comparator circuit (2) compares the date (5-2a) indicative of the present or next state and generates a state flag (6-2b). The analyzer circuit (3) decodes a state flag (6-3a) and generates the control signal (7-3b) for controlling operation of the arithmetic circuit (4). Based on a control signal (7-4a), the arithmetic circuit (4) operates on the data (5-4a) indicative of the present state and generates data (5-4b) indicative of the next state.

Dependencies are inferred from the claim text.