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US 2002/0161452 A1Published application
Hierarchical collective memory architecture for multiple processors and method therefor
OwnerMichael G. Peltierinventor
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Abstract
A method and means which allow multiple processors to operate efficiently as a single system while providing some autonomy for individual tasks is disclosed. The current invention further provides an architecture that is virtually infinitely scalable without reaching a limitation in throughput, which is normally associated with multiple processor architectures.
Claims6
A data processing system comprising, in combination:
- a plurality of processors;
- a local memory bus;
- local memory coupled to at least one of the plurality of processors via the local memory bus;
- shared memory coupled to the plurality of processors;
- a common memory bus coupled to the shared memory;
- and
- at least one address translator coupled to the plurality of processors and the shared memory for converting local bus addresses presented on the local memory bus to a larger address range which is applied to the common memory bus and the shared memory.
4 more elements
A data processing system comprising, in combination:
- a memory bus;
- at least one common memory storage device coupled to the memory bus;
- a plurality of nodes coupled to the memory bus wherein each of the plurality of nodes comprises:
- a processor which generates a data signal, an address signal, memory control signals, and block address configuration signals;
- a local bus coupled to the processor;
- a local memory device coupled to the processor;
- a configuration bus coupled to the processor;
- and
- an address translator for generating address signals on the memory bus based on stored values.
6 more elements
Dependencies are inferred from the claim text.