Double-layered low dielectric constant dielectric dual damascene method

A method of forming dual damascene openings in the fabrication of an integrated circuit device comprising:

• providing metal lines covered by an insulating layer overlying a semiconductor substrate;
• depositing a first organic dielectric layer overlying said insulating layer;
• depositing a second inorganic dielectric layer overlying said first dielectric layer;
• etching a trench pattern into said second dielectric layer;
• and
• thereafter etching a via pattern through said second inorganic dielectric layer and said first organic dielectric layer to complete said forming of said dual damascene openings in the fabrication of said integrated circuit device.

A method of forming dual damascene openings in the fabrication of an integrated circuit device comprising:

• providing metal lines covered by an insulating layer overlying a semiconductor substrate;
• depositing a first organic dielectric layer overlying said insulating layer;
• depositing a second inorganic dielectric layer overlying said first dielectric layer;
• etching a via pattern into said second dielectric layer;
• and
• simultaneously etching said via pattern into said first dielectric layer and etching a trench pattern into said second inorganic dielectric layer to complete said forming of said dual damascene openings in the fabrication of said integrated circuit device.

A method of forming dual damascene openings in the fabrication of an integrated circuit device comprising:

• providing metal lines covered by an insulating layer overlying a semiconductor substrate;
• depositing a first inorganic dielectric layer overlying said insulating layer;
• depositing a second organic dielectric layer overlying said first dielectric layer;
• etching a via pattern into said second dielectric layer;
• etching said via pattern into said first dielectric layer using patterned said second dielectric layer as a mask;
• and
• thereafter etching a trench pattern into said second inorganic dielectric layer to complete said forming of said dual damascene openings in the fabrication of said integrated circuit device.

A method of forming dual damascene openings in the fabrication of an integrated circuit device comprising:

• providing metal lines covered by an insulating layer overlying a semiconductor substrate;
• depositing a first inorganic dielectric layer overlying said insulating layer;
• depositing a second organic dielectric layer overlying said first dielectric layer;
• etching a trench pattern into said second dielectric layer;
• and
• thereafter etching a via pattern through said second inorganic dielectric layer and said first organic dielectric layer to complete said forming of said dual damascene openings in the fabrication of said integrated circuit device.

A method of forming dual damascene openings in the fabrication of an integrated circuit device comprising:

• providing metal lines covered by an insulating layer overlying a semiconductor substrate;
• depositing a first inorganic dielectric layer overlying said insulating layer;
• depositing a second organic dielectric layer overlying said first dielectric layer;
• etching a via pattern into said second dielectric layer;
• and
• simultaneously etching said via pattern into said first dielectric layer and etching a trench pattern into said second inorganic dielectric layer to complete said forming of said dual damascene openings in the fabrication of said integrated circuit device.