High coupling ratio stacked-gate flash memory and the method of making the same
OwnerHorng-Huei Tsenginventor
Life of this patent
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Abstract
A stacked-gate flash memory cell includes a trench formed in a substrate and a tunneling oxide is formed on the substrate. A first part of the floating gate is formed on the tunneling dielectric layer. A protruding isolation filler is formed in the trench and protruding over the upper surface of the first part of the floating gate, thereby forming a cavity between the two adjacent raised isolation filler. A second part of the floating gate is formed along the surface of the cavity to have a U-shaped structure in cross sectional view. A dielectric layer is conformally formed on the surface of the second part of the floating gate and a control gate is formed on the dielectric layer.
Claims12
A stacked-gate flash memory comprising:
- a substrate having trenches formed therein;
- a tunneling oxide formed on a surface of said substrate and adjacent to said trenches;
- raised isolation fillers formed in said trenches and protruding over an upper surface of said substrate, thereby forming a cavity between two adjacent raised isolation fillers;
- a floating gate formed along a surface of said cavity to have a U-shaped structure in cross sectional view, wherein the high level of said U-shaped structure is the same with the one of said raised isolation fillers;
- a dielectric layer conformally formed on a surface of said floating gate;
- and
- a control gate formed on said dielectric layer.
A method of manufacturing a stacked-gate flash memory, comprising:
- forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric;
- forming a first conductive layer on said first dielectric layer;
- forming a sacrificed layer on said first conductive layer;
- patterning said sacrificed layer, said first dielectric layer, said first conductive layer and said substrate to form trenches in said substrate;
- forming isolations into said trenches;
- removing said sacrificed layer, thereby forming a cavity between said isolations and said isolations protruding over said first conductive layer;
- forming a second conductive layer along a surface of said cavity and said isolation;
- removing a portion of said second conductive layer to a surface of said isolation, wherein said second conductive layer and said first conductive layer act as a floating gate;
- forming a second dielectric layer on a surface of said floating gate;
- and
- forming a third conductive layer on said second dielectric layer as a control gate.
Dependencies are inferred from the claim text.