Novel dram access transistor
AssigneeMicron Technology, Inc.
InventorsD. Mark Durcan, Roger Lee
Life of this patent
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Abstract
A method of forming memory devices, such as DRAM access transistors, having recessed gate structures is disclosed. Field oxide areas for isolation are first formed over a semiconductor substrate subsequent to which transistor grooves are patterned and etched in a silicon nitride layer. The field oxide areas adjacent to the transistor grooves are then recessed, so that subsequently deposited polysilicon for gate structure formation can be polished relative to the adjacent and elevated silicon nitride.
Claims35
A method of forming gate structures for a semiconductor device, comprising:
- forming an insulating layer over a semiconductor substrate;
- defining a first set of trenches in said semiconductor substrate and extending through said insulating layer;
- filling said first set of trenches with an insulating material to form isolation trenches;
- defining a second set of trenches in said semiconductor substrate which extend through said insulating layer in a direction orthogonal to said first set of trenches;
- etching regions of said isolation trenches to form recessed isolation trenches adjacent to said second set of trenches;
- forming a gate oxide within said second set of trenches;
- forming a conductive layer over said gate oxide and said recessed isolation trenches;
- and
- polishing said conductive layer relative to said recessed isolation trenches to form a conductive gate.
A method of forming a memory cell, comprising providing an insulating layer over a silicon substrate and forming a transistor including a gate structure fabricated within said silicon substrate, a source/drain region in said silicon substrate disposed adjacent to said gate structure, and a capacitor formed over said source/drain region, wherein said act of forming said gate structure further comprises:
- forming at least one isolation trench filled with an insulating material in said silicon substrate, said isolation trench extending through said insulating layer;
- defining at least one transistor trench in said silicon substrate which extends through said insulating layer in a direction orthogonal to said isolation trench;
- etching regions of said isolation trench to form at least one recessed isolation trench adjacent to said transistor trench;
- forming a gate oxide layer within said transistor trench;
- forming a conductive layer over said gate oxide layer and extending over said recessed isolation trench;
- polishing said conductive layer relative to said recessed isolation trench to form a conductive gate;
- and
- forming a protective layer over said conductive gate.
The method of claim 18, wherein said memory cell is a DRAM memory cell.
Dependencies are inferred from the claim text.