US 2002/0160563 A1 · Practical air dielectric interconnections by post-processing standard CMOS wafers

Abstract

A method of fabricating an integrated circuit having air-gaps between interconnect levels. In a preferred embodiment, an integrated circuit is partially fabricated. The partially fabricated integrated circuit includes a top layer, interconnect structures having a cladding layer, dielectric layers and an etch stop layer resistant to certain first types of etchants. The top layer of the integrated circuit is etched with a second type of etchant. The dielectric layers are then etched with one of the first types of etchants until the etch stop layer is reached. Thus, portions of the interconnect structures are exposed to create interconnect islands surrounded by air. A cover is mechanically placed over the exposed interconnect islands to protect the integrated circuit from dust particles.

Claims29

Dependent claims

A method of fabricating an integrated circuit having air-gap dielectric interconnects, comprising the steps of:

forming a partially fabricated integrated circuit comprising a top layer, interconnect structures having a cladding layer, dielectric layers separating some parts of said interconnect structures from each other and an etch stop layer resistant to a first etchant;
etching said top layer of said integrated circuit with a second etchant;
etching said dielectric layers with said first etchant until said etch stop layer is reached to expose portions of said interconnect structures to create interconnect islands;
and
mechanically introducing a cover over said exposed interconnect islands to protect said exposed interconnect islands.

2 more elements

Dependencies are inferred from the claim text.

Practical air dielectric interconnections by post-processing standard CMOS wafers

Life of this patent

Practical air dielectric interconnections by post-processing standard CMOS wafers

Life of this patent

Abstract

Claims29