Power down voltage control method and apparatus

A semiconductor device, comprising:

• a plurality of input buffers for buffering a plurality of DPD-type signals for signaling a power down (DPD) condition including a DPD enter/exit signal:
• an auxiliary buffer for separately buffering the DPD enter/exit signal;
• a plurality of voltage generators for supplying operating voltages to internal circuit;
• DPD control circuit for receiving the DPD-type signals to decode DPD enter and exit commands and for outputting a voltage generator control signal to turn off the voltage generators when DPD enter command is decoded, and to turn off the plurality of buffers excluding the auxiliary buffer;
• and
• an auto-pulse generator for generating a voltage pulse upon receiving the DPD exit command.

A semiconductor device, comprising:

• a plurality of voltage generators for supplying operating voltages to internal circuit;
• a power down (DPD) control circuit for receiving DPD-type signals to decode DPD enter and exit commands and for outputting a voltage generator control signal to turn off the voltage generators when DPD enter command is decoded;
• a power voltage detector for detecting the voltage output of at least one of the plurality of voltage generators for determining whether the one voltage generator is operating in power down mode;
• and
• an interlock circuit for receiving as inputs the DPD enter/exit signal and the output of the power voltage detector, and for outputting a DPD exit command when the DPD enter/exit signal signals a DPD exit mode and the one voltage generator outputs a voltage substantially at ground.

A method for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory, comprising;

• providing operating voltages to a plurality of voltage generators;
• detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory, wherein the plurality of voltage generators are turned off during DPD mode and turned on upon exit from DPD mode for providing operating voltages to internal circuitry of the semiconductor memory;
• and
• biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to maintain operation of the at least one of the plurality of voltage generators during DPD node.

A device for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory, comprising;

• means for providing operating voltages to a plurality of voltage generators;
• means for detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory wherein the plurality of voltage generators are turned off during DPD mode and turned on upon exit from DPD mode for providing operating voltages to internal circuitry of the semiconductor memory;
• and
• means for biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to mountain operation of the at least one of the plurality of voltage generators during DPD node.

A semiconductor device, comprising:

• a plurality of input buffers for buffering a plurality of DPD-type signals for signaling a power down (DPD) condition including a DPD enter/exit signal;
• a plurality of voltage generators for supplying operating voltages to internal circuit;
• means for receiving the DPD-type signals to decode DPD enter and exit commands and for outputting a voltage generator control signal to turn off the voltage generators and the plurality of buffers when DPD enter command is decoded;
• and
• means for generating a voltage pulse upon receiving the DPD exit command, wherein the pulse is used to initialize the internal circuit.