Dram cell reading method and device

A device for reading from a capacitive memory cell, including:

• a comparator of the voltage stored in the memory cell with respect to a reference value, which exhibits a high input impedance;
• a refreshment means distinct from the comparator, the refreshment means having a small output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell;
• and
• means for controllably connecting the refreshment means to the memory cell.

A memory circuit comprising:

• an array network of memory cells each including a selection switch connecting a capacitive element of the cell to a bit line and having a control terminal connected to a word line;
• a comparator selectively coupled to the bit line and configured to compare the voltage stored in the memory cell to a reference value, wherein the comparator exhibits a high input impedance;
• a refreshment means distinct from the comparator, the refreshment means having a small output impedance and being controlled by the comparator to impose a refreshment voltage to the memory cell;
• and
• means for controllably connecting the refreshment means to the memory cell.

A method, comprising:

• comparing a first voltage level, stored in a selected capacitive memory cell, with a second voltage level, stored in a reference memory cell, the comparing step including connecting a first input of a comparator having a high input impedance to the selected memory cell and connecting a second input of the comparator to the reference memory cell;
• restoring a voltage level representing a first logic level to the selected memory cell if the first voltage level exceeds the second voltage level;
• restoring a voltage level representing a second logic level to the selected memory cell if the second voltage level exceeds the first voltage level;
• restoring a voltage representing a reference voltage level to the reference memory cell;
• and
• each of the restoring steps including connecting an output of a restoring circuit to the respective one of the memory cells, the output having a low output impedance.

A device comprising:

• a selected capacitive memory cell having a first voltage level stored therein;
• a reference capacitive memory cell having a second voltage level stored therein;
• a comparator having a high input impedance;
• a circuit configured to connect the selected memory cell to a first input of the comparator and the reference memory cell to a second input of the comparator;
• and
• a circuit having an input coupled to an output of the comparator, having a low output impedance and configured to refresh the selected memory cell with a voltage representing a first logic level if the first voltage is greater than the second voltage, to refresh the selected memory cell with a voltage representing a second logic level if the second voltage is greater than the first voltage and configured to refresh the reference memory cell with a reference voltage.