MRAM semiconductor memory configuration with redundant cell arrays
AssigneeInfineon Technologies AG
InventorsStefan Lammers, Dietmar Gogl, Gerhard Muller
Life of this patent
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Abstract
The MRAM semiconductor memory configuration has MRAM main cell arrays in the form of a crosspoint array or a transistor array together with redundant MRAM cell arrays formed of redundant MRAM memory cells arranged in a plurality of planes and provided on the same chip. The redundant MRAM cell arrays are distributed over the individual planes of the memory matrix or one plane of the memory array is used in its entirety for providing redundant cell arrays.
Claims16
An MRAM semiconductor memory configuration, comprising:
- a memory matrix of a plurality of MRAM main cell arrays arranged in a crosspoint array or a transistor array and a plurality of redundant MRAM cell arrays formed with redundant MRAM memory cells, said plurality of MRAM main cell arrays together with said plurality of redundant MRAM cell arrays being disposed in a plurality of planes commonly integrated in a given chip;
- and
- wherein said redundant MRAM cell arrays are distributed over individual said planes of said memory matrix such that defective memory cells in one plane can be replaced with redundant memory cells from other planes.
In an MRAM semiconductor memory configuration having a memory matrix of a plurality of MRAM main cell arrays arranged in a crosspoint array or a transistor array and a plurality of redundant MRAM cell arrays formed with redundant MRAM memory cells, said plurality of MRAM main cell arrays together with said plurality of redundant MRAM cell arrays being disposed in a plurality of planes commonly integrated in a given chip, the improvement which comprises:
- one of said plurality of planes of the MRAM semiconductor memory configuration is used in an entirety thereof for providing redundant cell arrays.
Dependencies are inferred from the claim text.