System of performing a repair analysis for a semiconductor memory device having a redundant architecture
AssigneeHynix Semiconductor Inc.
InventorsSang Wook Park, Joo Hyung Mun, Hyeok Man Kwon
Life of this patent
Estimating the term…
Abstract
Two temporary buffers are employed alternatively storing a fail address data designated from a test operation, in which one of the temporary buffers transfers the fail address data to a data buffer in order to perform a repair analysis while the other one is storing the fail address data. Accordingly, the test and repair analysis operations are simultaneously performed. The capability of the rearrangement that includes the movement and exchange between the column and row fail address data enhances redundancy efficiency and yields of the memory device.
Claims27
A semiconductor memory device comprising:
- a test means for performing a test operation for an alternative one of row and column, detecting defective cells on the alternative unit of the row and column;
- and
- a repair analysis means for performing a repair analysis in which a fail address data involved in defective cells on the alternative one of the row and column are rearranged with including moving and exchanging between the fail address data in a unit of row and column.
A semiconductor memory device having a repair analysis means for fail address data assigned to defective cells on an alternative one of row and column and detected by performing a scanning test for the alternative one of the row and column, includes;
- a temporary buffer unit having a plurality of temporary buffers storing the fail address data for the defective cells;
- a data buffer receiving the fail address data stored in one of the temporary buffers;
- a data storage means receiving the fail address data from the data buffer and rearranging a structure of the fail address data;
- and
- a controller for controlling operations of the temporary buffer unit, the data buffer and the data storage means.
A method of performing a repair analysis with fail address data assigned to defective cells on an alternative one of row and column in a semiconductor memory device, comprising:
- storing the fail address data for defective cells detected in the test step for the alternative one of the row and column into a temporary buffer unit;
- storing the fail address data stored in the temporary buffer unit into a data buffer;
- writing the fail address data stored in the data buffer into the storage block;
- and
- moving and exchanging the fail address data stored in the storage block.
Dependencies are inferred from the claim text.