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US 2002/0159306 A1Published application
Ferroelectric memory device
AssigneeSeiko Epson Corporation
InventorsKazumasa Hasegawa, Eiji Natori, Hiromu Miyazawa, Junichi Karasawa
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Abstract
A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor formed of the first electrode, the second electrode, and ferroelectric layer is within the range of 0.1 P(+Vs)<P(−⅓Vs) when the applied voltage is changed from +Vs to −⅓Vs, and 0.1 P(−Vs)>P(+⅓Vs) when the applied voltage is changed from −Vs to +⅓Vs.
Claims21
A ferroelectric memory device comprising:
- a memory cell array, in which memory cells are arranged, in a matrix, which comprises first signal electrodes, second signal electrodes arranged in a direction which intersects with the first signal electrodes, and a ferroelectric layer disposed at least in intersecting regions in which the first signal electrodes intersect with the second signal electrodes,
- wherein, provided that the maximum absolute value of a voltage applied between one of the first signal electrodes and one of the second signal electrodes is Vs, a polarization value P of a ferroelectric capacitor comprising one of the first electrodes, one of the second electrodes, and the ferroelectric layer is within the range of:
- 0.1P(+Vs)<P(−⅓Vs)
- when the applied voltage is changed from +Vs to −⅓Vs, and
- 0.1P(−Vs)>P(+⅓Vs)
- when the applied voltage is changed from −Vs to +⅓Vs.
3 more elements
Dependencies are inferred from the claim text.