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US 2002/0159303 A1Published application
Asynchronous, High-bandwidth memory component using calibrated timing elements
AssigneeRambus Inc.
InventorsFrederick A. Ware, Ely K. Tsern, Craig E. Hampel, Donald C. Stark
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Abstract
Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
Claims96
A memory device comprising:
- one or more address registers that load a received memory address at a time indicated by a received input load signal;
- one or more delay elements that asynchronously generate a data register load signal at a predetermined time after the received input load signal;
- and
- one or more data registers that load memory data at a time indicated by the data register load signal.
1 more element
A memory device comprising:
- one or more address registers that load a received memory address at a time indicated by a received input load signal;
- an output bus;
- one or more delay elements that asynchronously generate a data enable signal at a predetermined time after the received input load signal to present read data on the output bus.
A memory device comprising:
- one or more address registers that load a received memory address at a time indicated by a received input load signal;
- one or more data registers that load memory data at a time indicated by an asynchronously received data register load signal.
A memory device comprising:
- one or more address registers that load a received memory address at a time indicated by a received input load signal;
- an output bus;
- an output driver that is responsive to a asynchronously received enable signal to present read data on the output bus.
A memory device comprising:
- a memory array that is accessed by sensing a memory row and then accessing one or more memory columns of the sensed memory row;
- a plurality of delay elements that are responsive to input load signals to produce corresponding sequences of asynchronously timed register load signals;
- a sequence of address registers that receive addresses and that advance the addresses through the address registers in response to the sequences of asynchronously timed register load signals;
- and
- wherein the memory array is responsive to addresses that have advanced through the sequence of address registers.
2 more elements
A wave-pipelined memory system comprising
- a memory controller;
- a plurality of memory devices;
- at least one bus extending between the memory controller and the plurality of memory devices, the bus having a propagation delay;
- wherein the memory devices and memory controller drive signals on the bus, at least some of said signals having durations that are shorter than the propagation delay of the bus;
- one or more input load signal lines that extends between the memory controller and at least a particular one of the memory devices, the one or more input load signal lines carrying an input load signal that initiates a memory access cycle in said particular one of the memory devices;
- said particular one of the memory devices being responsive to the input load signal to load memory data at a predetermined, asynchronous time following the input load signal.
3 more elements
A memory device comprising:
- memory access logic that receives memory access initiation signals and performs pipelined memory access cycles in response, the memory access logic having pipeline elements that are signaled in sequence to complete the memory access cycles;
- matched delay elements that are collectively adjustable to produce matching delays that are asynchronous within the memory device;
- the matched delay elements being configured to produce asynchronously timed pipeline load signals in response to the memory access initiation signals, to load the pipeline elements of the memory access logic in sequence.
A method of memory access comprising:
- receiving successive memory access initiation signals;
- asynchronously pipelining a plurality of memory access operations in response to the memory access initiation signals.
A memory device comprising:
- one or more address registers that load a received memory address at a time indicated by a received input load signal;
- one or more delay elements that asynchronously delay the received input load signal;
- a memory access logic that is responsive to the delayed input load signal to perform a memory operation;
- wherein the delay elements are calibrated to one or more calibration signals received from a source external to the memory device.
1 more element
Dependencies are inferred from the claim text.