DRAM word line voltage control to insure full cell writeback level
AssigneeInternational Business Machines Corporation
InventorsWayne F. Ellis, Russell J. Houghton, Mark D. Jacunski, Thomas M. Maffitt, William R. Tonti
Life of this patent
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Abstract
A DC analog circuit which monitors a DRAM sample cell access device and outputs a DC reference voltage to the word line voltage regulation system. The resulting output voltage from the word line voltage regulation system will then vary in accordance with the cell access device parametrics so as to guarantee a full high level will always be written into the DRAM cell.
Claims37
A method of biasing and monitoring a sample cell access device for regulating the word line selection voltage of a dynamic random access memory (DRAM) chip, said method comprising:
- (a) providing a sample cell access device wherein said sample cell access device substantially tracks the process parametric fluctuations of any one of a plurality of memory cell access devices within the DRAM chip;
- (b) forcing a constant DC current through said sample cell access device;
- (c) providing a DC voltage equal to the bitline selected voltage applied to a first terminal of said sample cell access device;
- and
- (d) providing an amplifying circuit connected between the gate terminal and a second terminal of said sample cell access device for regulating the voltage at the second terminal of said sample access device at a predetermined voltage greater than or less than the bitline selected voltage wherein said amplifying circuit outputs a reference voltage.
A word line voltage control circuit for monitoring a sample cell access device and regulating a word line voltage selection level of a dynamic random access memory (DRAM) cell, said word line voltage control circuit comprising:
- a sample cell access device;
- a circuit for forcing a fixed current through said sample cell access device;
- an amplifier circuit connected to the output of said sample cell access device;
- a feedback loop between said amplifier circuit and an input of said sample cell access device;
- and
- an output from said amplifier circuit to said word line of a dynamic random access memory (DRAM) cell.
A method of employing a word line voltage control circuit for monitoring a sample cell access device and regulating a word line voltage selection level of a dynamic random access memory (DRAM), said method comprising:
- providing a word line voltage control circuit;
- providing a sample cell access device;
- forcing a fixed current through said sample cell access device;
- providing an amplifier circuit connected to the output of said sample cell access device;
- providing a feedback loop between said amplifier circuit and an input of said sample cell access device;
- and
- providing an output from said amplifier circuit to said word line of a dynamic random access memory (DRAM) cell.
A word line voltage control circuit for monitoring a sample cell access device and regulating a word line voltage selection level of a dynamic random access memory (DRAM) cell, said word line voltage control circuit comprising:
- a sample cell access device;
- a circuit for forcing a fixed current through said sample cell access device;
- an inverting amplifier connected to the output of said sample cell access device;
- a level monitor connected to the output of said inverting amplifier;
- a charge pump connected to the output of said level monitor;
- a feedback loop between said charge pump and an input of said sample cell access device;
- and
- an output from said feedback loop to said word line of a dynamic random access memory (DRAM) cell.
A method of employing a word line voltage control circuit for monitoring a sample cell access device and regulating a word line voltage selection level of a dynamic random access memory (DRAM), said method comprising:
- providing a word line voltage control circuit;
- providing a sample cell access device;
- forcing a fixed current through said sample cell access device;
- providing an inverting amplifier connected to the output of said sample cell access device;
- providing a level monitor connected to the output of said inverting amplifier;
- providing a charge pump connected to the output of said level monitor;
- providing a feedback loop between said charge pump and an input of said level monitor;
- and
- providing an output from said feedback loop to said word line of a dynamic random access memory (DRAM) cell.
A dynamic random access memory (DRAM) word line supply comprising:
- (a) a voltage supply Vpp increasing from a voltage level insufficient to enable a memory cell access transistor for the word line toward a voltage level sufficient to enable said access transistor, for connection to the word line from time to time;
- (b) the memory cell access transistor for connecting a memory cell capacitor to a bitline, having a gate connected to the word line;
- (c) a sample transistor similar to the memory cell access transistor;
- (d) a circuit for applying the increasing voltage supply to the sample transistor for causing the sample transistor to conduct, under voltage supply conditions similar to those required by the memory cell access transistor;
- (e) a circuit for prohibiting increase of the voltage supply upon turn-on of the sample transistor;
- whereby the voltage supply having the voltage level sufficient to turn-on the memory cell access transistor is provided for connection to the word line.
A semiconductor structure including a word line voltage control circuit for monitoring and regulating a voltage signal to a word line of a dynamic random access memory (DRAM) cell, said semiconductor structure comprising:
- a substrate;
- at least one access transistor on said substrate;
- at least one buried node electrically coupled to said access transistor;
- at least one monitor transistor electrically coupled to said buried node;
- and
- an access transistor bitline connection electrically coupled to said buried node.
A word line voltage control circuit for monitoring and regulating a voltage signal to a word line of a dynamic random access memory (DRAM) cell, said word line voltage control circuit comprising:
- a compensated reference voltage system;
- and
- a word line voltage regulation system.
A word line voltage control circuit for monitoring a sample cell access device and regulating a word line voltage selection level of a dynamic random access memory (DRAM) cell, said word line voltage control circuit comprising:
- a sample cell access device;
- a comparator circuit for comparing a reference voltage output of the sample cell access device with a fixed reference voltage;
- at least one charge pump connected to the output of said sample cell access device, said at least one charge pump receiving an input from said comparator circuit;
- a feedback loop between said charge pump and an input of said sample cell access device;
- and
- an output from said feedback loop to said word line of a dynamic random access memory (DRAM) cell.
Dependencies are inferred from the claim text.