Data transfer circuit and semiconductor integrated circuit having the same

The semiconductor integrated circuit comprising:

• a memory cell array having a plurality of memory cells arranged in a matrix;
• an input/output control circuit for outputting data held in a selected memory cell designated on the basis of an address signal out of said memory cell;
• a data buffer circuit for outputting a reading data read from said input/output control circuit to an external output-terminal
• a data transfer circuit placed between said input/output control circuit and said data buffer circuit and for transmitting said reading data to said data buffer circuit
• a first input/output line for transmitting said reading data from said input/output control circuit to said data transfer circuit and
• a second input/output line for transmitting said reading data from said data transfer circuit to said data buffer circuit, and
• said data transfer circuit includes;
• three data signal lines are longer than said first and second input/output line;
• a first selection circuit for selecting two data signal lines whose potentials change to first and second potentials which are complementary to each other in accordance with said data to be transmitted out of said three data signal lines and for precharging a non-selected data signal line to said first potential;
• a second selection circuit for selectively and electrically connecting said two data signal lines selected by said first selection circuit out of said three data signal lines to a reception side circuit;
• and
• said first selection circuit having a driver circuit provided corresponding to each of said three data signal lines and connected between said first potential and third potentials and
• said logic control section for selecting two data signal lines out of said three data signal lines in conjunction with selecting one of said first potential and third potential supplied by said potential supply source to each of said three data signal lines
• and said driver circuit activates on the basis of a driver enable signal, and
• said second potential is set by a period of time during supplying said driver enable signal said second selection circuit having an amplifying circuit for amplifying a potential difference between said two data signal lines selected by said first selection circuit out of said three data signal lines, and
• on the basis of the potential difference amplified by said amplifying circuit, selectively and electrically connects said two data signal lines having selected by said first selection circuit to said second input/output line.