High speed decoder for flash memory

Addressing circuitry for block-type flash memories, comprising:

• a) a global word line associated with each row of blocks;
• and
• b) a local word line associated with each row of memory cells within a block;
• c) said local word line being powered by a vertical word line driver including a pair of series-connected transistors whose control gates are controlled by a global word line driver;
• d) the timing of said drivers being so arranged that said control gates are actuated on a predetermined time before the source-drain circuit of said transistors is powered, whereby the voltage built up in the transistors' channel capacitance by actuation of said control gates provides a turn-on boost for said transistors when their source-drain circuit becomes powered.

In a flash memory laid out in an array of blocks each containing an array of core cells, each row of blocks being associated with a separate global word line with positive and negative rails, each row of cells within a block having a local word line, and each row of cells within a block being associated with a separate vertical word line, a local xdecoder comprising:

• a) first and second n-transistors connected in series between one of said vertical word lines and ground, said local word line being connected between said first and second transistors;
• b) the gate of said first transistor being connected to the positive rail of said global word line through a word line gate transistor;
• and
• c) the gate of said second transistor being connected to the negative rail of said global word line.

A global xdecoder for outputting a positive rail and a negative rail of a global word line, comprising:

• a) a decode gate whose output is high when selected;
• b) a source of address transition detection signals which pulses high following selection of an address;
• c) a source of boost voltage, said source being at Vcc supply voltage during the address transition detection pulse but rising to a boost voltage following the address transition detection pulse;
• d) a p-channel transistor and an n-channel transistor connected in series from said boost voltage source to ground, the gates of said transistors being connected together and being operatively connected to the output of said decode gate;
• e) said positive rail of said global word line being connected to the interconnection of the source-drain circuits of said transistors;
• f) a p-channel boosting transistor connected between said boost voltage source and said connected gates of said first-named transistors, the gate of said boosting transistor being connected to said positive rail;
• g) a NOR gate whose inputs are the output of said decode gate and said address transition detection pulse, and
• h) an inverter connected to invert the output of said NOR gate to form said negative rail of said global word line.

A word line gate driver for flash memories, comprising:

• a) a word line gate signal output;
• b) a vertical block select decode gate, the output of said gate being high when the vertical block corresponding to said word line gate is selected;
• c) a source of boost voltage, said source being at Vcc supply voltage during the address transition detection pulse but rising to a boost voltage following the address transition detection pulse;
• d) a p-channel transistor and an n-channel transistor connected in series from said boost voltage source to ground, the gates of said transistors being connected together and being operatively connected to the output of said decode gate;
• e) a p-channel boosting transistor connected between said boost voltage source and said connected gates of said first-named transistors, the gate of said boosting transistor being connected to the interconnection of the source-drain circuits of said first-named transistors;
• f) p-channel and n-channel switching transistors having their gates connected to said interconnection of the source-drain circuits of said first-named transistors;
• g) the source-drain circuit of said p-channel switching transistor being connected between said boost voltage source and said word line gate signal output;
• and
• h) the source-drain circuit of said n-channel switching transistor being connected between said Vcc supply voltage and said word line gate signal output.

A vertical xdecoder for flash memories, comprising:

• a) a vertical word line signal output;
• b) a vertical word line select decode gate, said gate being a NAND gate with selection line inputs and an additional input;
• c) said additional input being connected to a detection pulse so delayed that said additional input goes low at the leading edge of said pulse but goes high a predetermined length of time after the trailing edge of said pulse:
• d) a source of boost voltage, said source being at Vcc supply voltage during the address transition detection pulse but rising to a boost voltage following the address transition detection pulse;
• e) a p-channel transistor and an n-channel transistor connected in series from said boost voltage source to ground, the gates of said transistors being connected together and being operatively connected to the output of said decode gate;
• f) a p-channel boosting transistor connected between said boost voltage source and said connected gates of said first-named transistors, the gate of said boosting transistor being connected to said vertical word line signal output;
• and
• g) said vertical word line signal output being connected to the interconnection between said first-named transistors in their source-drain circuit.