Higher program vt and faster programming rates based on improved erase methods
AssigneeAdvanced Micro Devices, Inc.
InventorsDarlene G. Hamilton, Narbeh Derhacobian, Janet S. Y. Wang, Kulachet Tanpairoj
Life of this patent
Estimating the term…
Loading patent…
AssigneeAdvanced Micro Devices, Inc.
InventorsDarlene G. Hamilton, Narbeh Derhacobian, Janet S. Y. Wang, Kulachet Tanpairoj
Estimating the term…
A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.
A method of programming a bit of an ONO dual bit memory cell, the method comprising:
A method of determining a delta VT for programming bits of an array of ONO dual bit memory cells, the method comprising:
A system for programming bits in an array of ONO dual bit memory cells, the system comprising:
A system for programming bits in an ONO dual bit memory cell, comprising:
Dependencies are inferred from the claim text.