Flash memory with nanocrystalline silicon film floating gate
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of nanocrystalline silicon particles. Each nanocrystalline silicon particle has a diameter of about 10 Å to 100 Å. The nanocrystalline silicon particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.
Claims27
A method of storing data in a memory cell, comprising:
- applying a first voltage to a control gate of a memory cell, the memory cell further comprising a source, a drain and a floating gate, wherein the floating gate comprises a conductive film of nanocrystalline silicon particles, further wherein the nanocrystalline silicon particles are in contact to form the conductive film;
- applying a second voltage to the drain of the memory cell;
- applying a third voltage to the source of the memory cell;
- and
- trapping electrons on the floating gate.
A method of storing data in a memory cell, comprising:
- applying a first voltage to a control gate of a memory cell, the memory cell further comprising a source, a drain and a floating gate, wherein the floating gate comprises a conductively-doped film of nanocrystalline silicon particles, further wherein the nanocrystalline silicon particles are in contact to form the conductively-doped film;
- applying a second voltage to the drain of the memory cell;
- applying a third voltage to the source of the memory cell;
- and
- trapping electrons on the floating gate.
A method of erasing data in a memory cell, comprising:
- applying a first voltage to a control gate of a memory cell, the memory cell further comprising a source, a drain and a floating gate, wherein the floating gate comprises a conductive film of nanocrystalline silicon particles, further wherein the nanocrystalline silicon particles are in contact to form the conductive film;
- applying a second voltage to the source of the memory cell;
- electrically floating the drain of the memory cell;
- and
- removing electrons from the floating gate.
A method of erasing data in a memory cell, comprising:
- applying a first voltage to a control gate of a memory cell, the memory cell further comprising a source, a drain and a floating gate, wherein the floating gate comprises a conductively-doped film of nanocrystalline silicon particles, further wherein the nanocrystalline silicon particles are in contact to form the conductively-doped film;
- applying a second voltage to the source of the memory cell;
- electrically floating the drain of the memory cell;
- and
- removing electrons from the floating gate.
A method of storing data in a memory cell, comprising:
- applying a first voltage to a control gate of a memory cell, the memory cell further comprising a source, a drain and a floating gate, wherein the floating gate comprises a conductive film of nanocrystalline silicon particles each having a general diameter in a range of about 10 Å to 100 Å, further wherein the nanocrystalline silicon particles are in contact to form the conductive film;
- applying a second voltage to the drain of the memory cell;
- applying a third voltage to the source of the memory cell;
- and
- trapping electrons on the floating gate.
A method of storing data in a memory cell, comprising:
- applying a first voltage to a control gate of a memory cell, the memory cell further comprising a source, a drain and a floating gate, wherein the floating gate comprises a conductively-doped film of nanocrystalline silicon particles each having a general diameter in a range of about 10 Å to 100 Å, further wherein the nanocrystalline silicon particles are in contact to form the conductively-doped film;
- applying a second voltage to the drain of the memory cell;
- applying a third voltage to the source of the memory cell;
- and
- trapping electrons on the floating gate.
A method of erasing data in a memory cell, comprising:
- applying a first voltage to a control gate of a memory cell, the memory cell further comprising a source, a drain and a floating gate, wherein the floating gate comprises a conductive film of nanocrystalline silicon particles each having a general diameter in a range of about 10 Å to 100 Å, further wherein the nanocrystalline silicon particles are in contact to form the conductive film;
- applying a second voltage to the source of the memory cell;
- electrically floating the drain of the memory cell;
- and
- removing electrons from the floating gate.
A method of erasing data in a memory cell, comprising:
- applying a first voltage to a control gate of a memory cell, the memory cell further comprising a source, a drain and a floating gate, wherein the floating gate comprises a conductively-doped film of nanocrystalline silicon particles each having a general diameter in a range of about 10 Å to 100 Å, further wherein the nanocrystalline silicon particles are in contact to form the conductively-doped film;
- applying a second voltage to the source of the memory cell;
- electrically floating the drain of the memory cell;
- and
- removing electrons from the floating gate.
Dependencies are inferred from the claim text.