Back to results
US 2002/0158829 A1Published application
Display system
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei Yamazaki, Jun Koyama
Life of this patent
Estimating the term…
Abstract
To solve a problem of increased power consumption power due to wiring capacitances, which occurs when connecting onto a display substrate a substrate on which a memory, a memory controller, and the like are formed. The memory, the memory controller, and the like are integrally formed on the display substrate. At this time, these circuits are formed using a dual gate TFT. Thus, a display device in which wiring capacitances of connection portions between driver circuits composing a display and the memory controller and the like are reduced and which has thus low power consumption can be provided.
Claims46
A display system comprising:
- a plurality of pixels comprising a plurality of first thin film transistors over a substrate having an insulating surface;
- a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a plurality of second thin film transistors over the substrate;
- and
- a first means for storing the image signal to be outputted to the driver circuit, the first means comprising a plurality of third thin film transistors over the substrate,
- wherein each of the plurality of first to third thin film transistors comprises a first electrode and a second electrode overlapped with a channel region through an insulating film, and
- wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the channel region therebetween.
3 more elements
A display system comprising:
- a plurality of pixels comprising a plurality of first thin film transistors over a substrate having an insulating surface;
- a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a plurality of second thin film transistors over the substrate;
- and
- a first means for storing the image signal to be outputted to the driver circuit, the first means comprising a plurality of third thin film transistors over the substrate,
- a second means for determining a drive frequency of the driver circuit, the second means comprising a plurality of fourth thin film transistors over the substrate,
- wherein each of the plurality of first to fourth thin film transistors comprises a first electrode and a second electrode overlapped with a channel region through an insulating film, and
- wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the channel region therebetween.
4 more elements
A display system comprising:
- a plurality of pixels comprising a plurality of first thin film transistors over a substrate having an insulating surface;
- a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a plurality of second thin film transistors over the substrate;
- and
- a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a plurality of third thin film transistors over the substrate,
- wherein each of the plurality of first to third thin film transistors comprises a first electrode and a second electrode overlapped with a channel region through an insulating film, and
- wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the channel region therebetween.
3 more elements
A display system comprising:
- a plurality of pixels comprising a plurality of first thin film transistors over a substrate having an insulating surface;
- a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a plurality of second thin film transistors over the substrate;
- and
- a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a plurality of third thin film transistors over the substrate,
- a memory controller for assigning an address of the memory and outputting a write signal and a read signal, the memory controller comprising a plurality of fourth thin film transistors over the substrate,
- wherein each of the plurality of first to fourth thin film transistors comprises a first electrode and a second electrode overlapped with a channel region through an insulating film, and
- wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the channel region therebetween.
4 more elements
A display system comprising:
- a plurality of pixels comprising a plurality of first thin film transistors over a substrate having an insulating surface;
- a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a plurality of second thin film transistors over the substrate;
- and
- a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a plurality of third thin film transistors over the substrate,
- a memory controller for assigning an address of the memory and outputting a write signal and a read signal, the memory controller comprising a plurality of fourth thin film transistors over the substrate,
- a CPU for outputting a signal to the memory controller, the CPU comprising a plurality of fifth thin film transistors over the substrate,
- wherein each of the plurality of first to fifth thin film transistors comprises a first electrode and a second electrode overlapped with a channel region through an insulating film, and
- wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the channel region therebetween.
5 more elements
A display system comprising:
- a plurality of pixels comprising a plurality of first thin film transistors over a substrate having an insulating surface;
- a driver circuit for outputting an inputted image signal to the plurality of pixels, the driver circuit comprising a plurality of second thin film transistors over the substrate;
- and
- a memory for storing the image signal to be outputted to the driver circuit, the memory comprising a plurality of third thin film transistors over the substrate,
- a memory controller for assigning an address of the memory and outputting a write signal and a read signal, the memory controller comprising a plurality of fourth thin film transistors over the substrate,
- a CPU for outputting a signal to the memory controller, the CPU comprising a plurality of fifth thin film transistors over the substrate,
- a display controller for outputting a clock pulse and a start pulse to the driver circuit, the display controller comprising a plurality of sixth thin film transistors over the substrate,
- wherein each of the plurality of first to sixth thin film transistors comprises a first electrode and a second electrode overlapped with a channel region through an insulating film, and
- wherein the first electrode and the second electrode are overlapped with each other so as to sandwich the channel region therebetween.
6 more elements
A display system comprising:
- a plurality of pixels each including a thin film transistor, the thin film transistor comprising:
- a semiconductor layer having at least a first channel region, a second channel region, and an impurity region between the first channel region and the second channel region, a first electrode, a second electrode, and a third electrode,
- wherein the first electrode is overlapped with the first channel region, the second channel region, and the impurity region through a first insulating film,
- the second electrode is overlapped with the first channel region through a second insulating film,
- the third electrode is overlapped with the second channel region through the second insulating film,
- the second electrode is overlapped with the first electrode so as to sandwich the first channel region therebetween, and
- the third electrode is overlapped with the first electrode so as to sandwich the second channel region therebetween.
4 more elements
Dependencies are inferred from the claim text.