Linear voltage subtractor/adder circuit and MOS differential amplifier circuit therefor

A voltage subtractor/adder circuit comprising:

• a differential pair having first and second MOS transistors, gate electrodes of said first and second MOS transistors forming input terminals for receiving an input differential voltage, drain electrodes of said first and second MOS transistors forming output terminals for outputting a subtraction output signal, and source electrodes of said first and second MOS transistors being commonly coupled to form an output terminal for addition output voltage;
• and
• a constant current source which drives said differential pair.

A MOS differential amplifier circuit comprising:

• a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of said first and second MOS transistors being commonly coupled and being driven by a current source;
• and
• wherein current value of said current source being controlled such that a difference voltage between a common mode voltage and a common source voltage of said first and second MOS transistors becomes a constant value.

A MOS differential amplifier circuit comprising:

• a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of said first and second MOS transistors being commonly coupled and being driven by a constant current source;
• and
• wherein a current is injected into said constant current source such that a difference voltage between a common mode voltage and a common source voltage of said first and second MOS transistors becomes a constant voltage.

A MOS differential amplifier circuit comprising:

• a MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of said first and second MOS transistors being commonly coupled and being driven by a constant current source;
• and
• third and fourth MOS transistors which are load transistors of said first and second MOS transistors, respectively, and whose gates receive the sum of a predetermined constant voltage and a voltage obtained by subtracting a common source voltage of said first and second MOS transistors from a common mode voltage.

A complementary MOS differential amplifier circuit comprising:

• MOS differential pair having first and second MOS transistors and receiving an input differential voltage, source electrodes of said first and second MOS transistors being commonly coupled and being driven by a first constant current source;
• a MOS quadri-tail cell having third, fourth, fifth and sixth MOS transistors which have different conductivity type from that of said first and second MOS transistors, source electrodes of said third, fourth, fifth and sixth MOS transistors being commonly coupled and being driven by a second constant current source;
• wherein gate electrodes of said fifth and sixth MOS transistors being coupled to a common source electrode of said first and second MOS transistors, drain electrodes of said fifth and third MOS transistors being commonly coupled and forming one output terminal, drain electrodes of said sixth and fourth MOS transistors being commonly coupled and forming the other output terminal, and gate electrodes of said first and second MOS transistors and gate electrodes of said third and fourth MOS transistors receiving input voltages.