# US 2002/0158684 A1 · Noise suppression circuitry and method

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- Number: US 2002/0158684 A1
- Document ID: US20020158684A1
- Status: Published application
- Kind: A1
- Application number: 09/846,523
- Filed: 2001-04-30
- Published: 2002-10-31
- Earliest claimed: 2001-04-30
- Assignees: STMicroelectronics S.r.l.
- Inventors: David C. McClure
- Web page: https://patentgrep.com/patent/US20020158684A1

## CPC

- G01R 19/16538: {in AC or DC supplies (G01R19/16519 and G01R19/16528 take precedence)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A circuit and method are disclosed for monitoring the voltage level of an electrical signal, such as an unregulated power supply. The circuit includes a comparator that compares the electrical to the voltage reference and generates an output having a value that is based upon the comparison. A oscillation suppression circuit receives the output of the comparator and generates an output signal that follows the output of the comparator once the output of the comparator remains stable and in the same logic state for a predetermined of time.

## Claims

### Claim 1

A power supply detect circuit, comprising:
a comparator for comparing a power supply signal and a reference voltage signal and generating an output signal based upon the comparison; and
a first circuit having an input coupled to the output of the comparator and an output signal driven to a first logic state upon the output of the comparator being in the same logic state substantially entirely over a plurality of consecutive time periods.

### Claim 2 (depends on 1)

The power supply detect circuit of claim 1, wherein:
the first circuit drives the output signal thereof to the first logic state upon the output of the comparator being in the first logic state substantially entirely over a plurality of consecutive time periods, and to a second logic state upon the output of the comparator being in the second logic state substantially entirely over a plurality of consecutive time periods.

### Claim 3 (depends on 2)

The power supply detect circuit of claim 2, wherein:
the first circuitry maintains the output signal thereof in the first logic state until the output of the comparator is in the second logic state substantially entirely over a plurality of consecutive time periods, and maintains the output signal in the second logic state until the output of the comparator is in the first logic state substantially entirely over a plurality of consecutive time periods.

### Claim 4 (depends on 1)

The power supply detect circuit of claim 1, wherein the first circuit comprises shift register circuitry.

### Claim 5 (depends on 4)

The power supply detect circuit of claim 4, wherein the shift register circuitry comprises:
a plurality of flip flop elements connected in a chain of flip flop element, a first flip flop element in the chain including a clocked synchronous input and an unclocked asynchronous input, the output of the comparator being coupled to the clocked and unclocked inputs of the first flip flop element.

### Claim 6 (depends on 5)

The power supply detect circuit of claim 5, wherein the unclocked input of the first flip flop element comprises an asynchronous reset input.

### Claim 7 (depends on 5)

The power supply detect circuit of claim 5, wherein the unclocked input of the first flip flop element comprises an asynchronous set input.

### Claim 8 (depends on 5)

The power supply detect circuit of claim 5 wherein the output of the first circuit is based upon a logic state of each flip flop element in the shift register circuitry.

### Claim 9 (depends on 8)

The power supply detect circuit of claim 8, wherein the first circuit further comprises:
a logic gate having an input coupled to an output of each flip flop element and an output; and
a transistor having a control terminal coupled to the output of the logic gate, and a conduction terminal coupled to the output signal of the first circuit.

### Claim 10 (depends on 9)

The power supply detect circuit of claim 9, wherein:
the first circuit further comprises a latching circuit coupled to the conduction terminal of the transistor for maintaining a logic state of the output signal of the first circuit when the transistor is shut off.

### Claim 11 (depends on 4)

The power supply detect circuit of claim 4, wherein the shift register circuitry comprises:
a first shift register including a plurality of flip flop elements and operating to assert a first signal when the output of the comparator remains in the first logic state substantially entirely over a plurality of consecutive time periods;
a second shift register including a plurality of flip flop elements and operating to assert a second signal when the output of the comparator remains in a second logic state substantially entirely over a plurality of consecutive time periods; and
driver circuitry for driving the output signal of the first circuit based upon the first and second signals.

### Claim 12 (depends on 11)

The power supply detect circuit of claim 11, wherein the driver circuitry comprises:
a high side driver having a control terminal coupled to the first signal; and
a low side driver having a control terminal coupled to the second signal, the high and low side drivers being adapted for driving the output signal of the first circuit.

### Claim 13

A method for monitoring an electrical signal, comprising:
receiving a digital signal; and
generating an output signal having a logic state that substantially matches the logic state of the digital signal upon the digital signal being in the same logic state substantially entirely over a predetermined period of time.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
initially comparing the voltage appearing on the electrical signal to a reference voltage and generating the digital signal based upon the comparison.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
during times when the digital signal is not in the same logic state substantially entirely over a predetermined period of time, maintaining the output signal in the last logic state the digital signal remained in for a predetermined period of time.

### Claim 16 (depends on 13)

The method of claim 13, wherein the step of generating comprises the steps of:
sampling the digital signal at a plurality of sampling times;
generating an internal signal for each sample of the digital signal; and
asynchronously controlling the logic level of the most recently generated internal signal based upon the logic level of the digital signal.

### Claim 17 (depends on 16)

The method of claim 16, wherein the step of generating the output signal comprises driving the output signal to the logic state upon the logic state of each sample and the logic state of the digital signal being the same.

### Claim 18

An integrated circuit, comprising:
a noise suppression circuit having an input coupled to receive a first signal and an output signal that is asserted when the first signal is in the asserted state substantially entirely over a predetermined period of time and de-asserted when the first signal is in a de-asserted state substantially entirely over a predetermined period of time.

### Claim 19 (depends on 18)

The integrated circuit of claim 18, wherein:
the noise suppression circuit comprises a first shift register circuit having an asynchronous input and a synchronous input coupled to the first signal.

### Claim 20 (depends on 19)

The integrated circuit of claim 19, wherein:
the second circuit further comprises a second shift register circuit having an asynchronous input and a synchronous input coupled to the first signal.

### Claim 21 (depends on 20)

The integrated circuit of claim 20, wherein:
the asynchronous input of the second shift register circuit is an asynchronous set input of a first flip flop element of the second shift register circuit.

### Claim 22 (depends on 20)

The integrated circuit of claim 20, wherein:
an output signal of the second shift register circuit is driven to a first logic state upon each flip flop element being in the same state, the output signal of the noise suppression circuit being de-asserted upon the output of the second shift register circuit being in the first logic state.

### Claim 23 (depends on 22)

The integrated circuit of claim 22, wherein:
an output signal of the first shift register circuit is driven to the second logic state upon each flip flop element being in the same state, the output signal of the noise suppression circuit being asserted upon the output of the first shift register circuit being in the first logic state.

### Claim 24 (depends on 20)

The integrated circuit of claim 20, wherein:
the asynchronous input of the first shift register circuit is an asynchronous set input of a first flip flop element of the first shift register circuit.

### Claim 25 (depends on 18)

The integrated circuit of claim 18, further comprising:
a compare circuit for comparing a voltage level of an electrical signal to a voltage reference and generating the first signal having a value that is based upon the comparison.

### Claim 26

A circuit for monitoring an electrical signal, comprising:
means for receiving a digital signal; and
means for generating an output signal having a logic state that substantially matches the logic state of the digital signal upon the digital signal being in the same logic state substantially entirely over a predetermined period of time.

### Claim 27 (depends on 26)

The circuit of claim 26, wherein:
during times when the digital signal is not in the same logic state substantially entirely over a predetermined period of time, the means f or generating maintains the output signal in the last logic state the digital signal remained in for a predetermined period of time.

### Claim 28 (depends on 26)

The circuit of claim 26, wherein the generating means comprises:
means for sampling the digital signal at a plurality of sampling times;
means generating an internal signal for each sample of the digital signal; and
means for asynchronously controlling the logic level of the most recently generated internal signal based upon the logic level of the digital signal.

### Claim 29 (depends on 28)

The circuit of claim 28, wherein the means for generating the output signal drives the output signal to the logic state upon the logic state of each sample and the logic state of the digital signal being the same.