Fast locking phase frequency detector
AssigneeALTERA CORPORATION, a corporation of Delaware
InventorsXiaobao Wang, Chiakang Sung, Joseph Huang, Bonnie I. Wang, Khai Nguyen, Wayne Yeung, In Whan Kim
Life of this patent
Estimating the term…
Abstract
A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.
Claims34
A circuit comprising:
- a first register having a first data input, a first clock input coupled to a first clock signal, and a first data output;
- a second register having a second data input coupled to the first data output, a second clock input coupled to the first clock signal, and a second data output;
- a third register having a third data input, a third clock input coupled to a second clock signal, and a third data output;
- a fourth register having a fourth data input coupled to the third data output, a fourth clock input coupled to the second clock signal, and a fourth data output;
- a first logic gate, coupled to the first and third data outputs, having a first logic output coupled to a first clear input of the first register;
- and
- a second logic gate, coupled to the second and third data outputs, having a second logic output coupled to a second clear input of the second register.
A phase locked loop circuit comprising:
- an m-state phase frequency detector coupled to a reference clock signal and a feedback clock signal, wherein m is an integer greater than 3;
- a charge pump coupled to the m-state phase frequency detector;
- a voltage controlled oscillator coupled to the charge pump, generating a clock output;
- a divider circuit receiving the clock output and generating the feedback clock.
A programmable logic integrated circuit comprising:
- a plurality of logic array blocks, programmably configurable to perform logical functions;
- a programmable interconnect structure coupled to the logic array blocks;
- and
- a phase locked loop circuit, receiving a first reference clock signal and generating a clock output programmably coupled to the logic array blocks, wherein the phase locked loop circuit comprises a phase frequency detector circuit having m states, where m is greater than 3.
A method of maintaining a phase relationship-between a first clock signal and a second clock signal comprising:
- providing a first UP output and a second UP output;
- generating a pulse at the first UP output when a first edge of the first clock signal leads a second edge of the second clock signal;
- and
- generating a pulse at the second UP output when a third edge of the first clock signal leads the second edge.
A method of maintaining a phase relationship between a first clock signal and a second clock signal comprising:
- providing a first DOWN output and a second DOWN output;
- generating a pulse at the first DOWN output when a first edge of the first clock signal leads a second edge of the second clock signal;
- and
- generating a pulse at the second DOWN output when a third edge of the first clock signal leads the second edge.
Dependencies are inferred from the claim text.