Domino circuit

A domino logic circuit contained within an integrated circuit comprising:

• a clock signal for controlling pre-charge and evaluation phases of the domino logic circuit,
• a dynamic logic circuit, the dynamic logic circuit having
• a first input port to receive the clock signal,
• a second input port to receive a logic signal,
• an output port to deliver a first evaluated signal to an intermediate logic circuit, the intermediate logic circuit having
• a first pull-up transistor having a gate input to receive a first control signal which is derived in reference to the clock signal,
• an n-block transistor having a gate input to receive the first evaluated signal from the dynamic logic block, the n-block transistor also having an output port to deliver a second evaluated signal to a target circuit, the n-block transistor also having a source terminal connected to a low ground voltage line,
• a delay element having an input port for receiving the first control signal input to the first pull-up transistor, the delay element also having an output port for delivering a delayed control signal to a logic gate,
• the logic gate having
• a first input port for receiving the delayed control signal,
• a second input port for receiving the second evaluated signal from the n-block transistor,
• an output port for delivering a second control signal to a second pull-up transistor, the second transistor having a gate input for receiving the second control signal.