Hybrid power supply circuit and method for charging/discharging a logic circuit using the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHo-rang Jang, Ki-won Jo
Life of this patent
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Abstract
A hybrid power supply circuit for supplying a power to a logic circuit performing a digital logic process and for controlling the charging/discharging of the logic circuit. The power supply circuit has an adiabatic power supply portion for charging/discharging the logic circuit in such a manner to suppress a sudden current change during initial time after the input signal changes, and a CMOS power supply portion for quickly charging/discharging the logic circuit to supply power level/ground level after the charging/discharging by the adiabatic power supply portion. The energy consumption of the circuit decreases even in a digital system having a plurality of logic circuits.
Claims14
A hybrid power supply circuit for supplying a power to a logic circuit performing a logic process in response to an input signal, and for charging/discharging the logic circuit, the hybrid power supply circuit comprising:
- an adiabatic power supply portion for charging/discharging the logic circuit in such a manner to suppress a sudden current change during a first predetermined time after the input signal changes;
- and
- a CMOS power supply portion for charging/discharging the logic circuit to supply power level/ground level more quickly than a charging/discharging speed by the adiabatic power supply during a second predetermined time following the first predetermined time.
A method for charging/discharging a logic circuit performing a digital logic algorithm in response to an input signal by using a hybrid power supply circuit having an adiabatic power supply portion and a CMOS power supply portion, the method comprising the steps of:
- charging/discharging the logic circuit according to an output thereof by using the adiabatic power supply portion during a first predetermined time after the input signal changes;
- and
- charging/discharging the logic circuit to a required level by using the CMOS power supply portion during a second predetermined time after the first predetermined time.
A method for charging/discharging a plurality of logic circuits in a digital system having the logic circuits operating synchronized to a system clock signal determined by a maximum delay time and a hybrid power supply circuit including an adiabatic power supply portion and a CMOS power supply portion for supplying a power to the logic circuits, the method comprising the steps of:
- (a) comparing all of the delay time of the logic circuits so as to determine the maximum delay time and comparing a delay time of a logic circuit to be charged/discharged with the maximum delay time;
- (b) charging/discharging the logic circuit to a required level by using the CMOS power supply portion if the delay time of the logic circuit is identical to the maximum delay time in step (a);
- (c) charging/discharging the logic circuit by using the adiabatic power supply portion during a first predetermined time if the delay time of the logic circuit under concern is shorter than the maximum delay time in step (a);
- and
- (d) charging/discharging the logic circuit to a supply power level or a ground level by using the CMOS power supply portion after the first predetermined time.
Dependencies are inferred from the claim text.